Noise

EE 201A
Noise Modeling
Jeff Wong and Dan Vasquez

Electrical Engineering Department
University of California, Los Angeles
EE 201A Modeling and Optimization for VLSI Layout
Efficient Coupled Noise Estimation

for On-Chip Interconnects
Anirudh Devgan
Austin Research Laboratory
IBM Research Division, Austin TX
MEMS Research Laboratory
Joe Zendejas and Jack W. Judy
Motivation
Noise failure can be more severe than timing
failure
Difficult to control from chip terminals
Expensive to correct (refabrication)
Circuit or timing simulation (like SPICE) can

be used
Linear reduction techniques can be applied for
linearly modeled circuits
i.e. moment matching methods
Inefficient for noise verification and avoidance

applications
Noise Estimation
The paper presents an electrical metric for
efficiently estimating coupled noise for onchip interconnects
Capacitive coupling between an aggressor
net and a victim net leads to coupled
noise
Aggressor net: switches states; source of
noise for victim net
Victim net: maintains present state; affected by
coupled noise from aggressor net
Circuit Schematic
Coupling
capacitors
CC = [CC,ii]
V2,1
V2,n
C2 = [C2,ii]
V1,1
V1,n
Switching
signal
Vs(t)
C1 = [C1,ii]
Lets analyze the case for one aggressor net and one victim net
Circuit Equations
Coupled equation for circuit:
C1
C
C
CC
C2
d
dt
d
dt
r
v1 t
A11
r
v2 t
A21
In Laplace domain:
r
C1 CC sV1 s
A11
r
C
C C2 sV2 s
A21
A12
A22
r
v1 t
r
v2 t
A12
A22
r
V1 s
r
V2 s
B1
B vs t
2
B1
B Vs s
2
Circuit Equations
Aggressor net:
r
r
r
r
sC1V1 sCCV2 A11V1 A12V2 B1Vs
r
r
1
V1 sC1 A11 A12 sCC V2 B1Vs
Victim net:
r
r
r
r
sCCV1 sC2V2 A21V1 A22V2 B2Vs
r
r
1
V2 sC2 A22 A21 sCC V1 B2Vs
Transfer Function
Transfer
function:
r
1
A21 sCC sC1 A11 B1 B2
V2
H s r
Vs sC2 A22 A21 sCC sC1 A11 1 A12 sCC
Simplifications (details later):
A12 0, A21 0, B2 0
Simplified
transfer function:
r
1
sCC sC1 A11 B1
V2
H s r
Vs sC2 A22 sCC 2 sC1 A11 1
Simplifications
A12 = 0
No resistive (or DC) path exists from the
aggressor net to the victim net
A21 = 0
No resistive (or DC) path exists from the victim
net to the aggressor net
B2 = 0
No resistive (or DC) path exists from the
voltage/noise source to the victim net
Maximum Induced Noise

H(s=0) = 0
Coupling between aggressor and victim
net is purely capacitive
Maximum induced noise can be
computed
Assume Vs is a finite or infinite ramp

lim
d
dt
r
r max
V2 0 V2 is finite
Maximum Induced Noise

Final value theorem:
r max
r
r
v2 t lim sV2 s
V2 lim
t
s 0
Ramp input u(s):
r max
sH s u s lim sH s
V2 lim
s 0
s 0
H s
&
u
&
lim
u
2
s
0
s
s
1
CC sC1 A11 B1
&
lim
u
2
1
s 0
sC2 A22 sCC sC1 A11
r max
V2
r max
1
V2 A22
CC A111 B1&
u
Circuit Interpretation
V&1ss
r max
1
1
V2 A22 CC A11 B1 &
u
IC
Switching
slope
Circuit Computations
(matrix method)
ss
1
&
u
Step 1: Compute V1 A11 B1&
Requires circuit analysis of the

aggressor net
r
ss
&
Step 2: Compute I C CCV1
Requires a matrix multiplication
r max
r
1
Step 3: Compute V2 A22 I C
Requires circuit analysis of the victim

net
(by inspection)
ss
1
&
u
Aggressor circuit transformation:
Replace input source with its derivative

Replace aggressor nets capacitors with
open circuits
(by inspection)
ss
1
&
u
Typical interconnects:
Negligible loss: no resistive path to ground
ss
&
V1 V&s
(by inspection)
r
r
Step 2: Compute I C CCV&1ss
Convert steady state derivative on the

aggressor net to a current on the victim
net
r
I C I i CC ,ijV&1ssj
i : index of node on the victim net

j : index of node on the aggressor net
(by inspection)
r max r max
r
1
Step 3: Compute N V2 A22 I C
Victim circuit transformation:
Replace capacitors with coupling currents

The voltage at each node corresponds to
that nodes maximum induced noise
(by inspection)
r max r max
r
1
Typical interconnects:
Compute by inspection in linear time
r max
max
max
VC Vi Ri I j Ni 1
Li
(by inspection)
r max r max
r
1
3RC Circuit example:
N imax Ri I j N imax
1
Li
N1max R1 I1 I 2 I 3
N 2max R1 I1 I 2 I 3 R2 I 2
N1max R1 I1 I 2 I 3 R3 I 3
Computation Costs
ss
&
V
Step 1: 1 V&s
No computation required
Step 2:
I i CC ,ijV&1ssj
j
Simple multiplications
Step 3:
N imax Ri I j N imax
1
Li
Simple multiplications
Multiple aggressor nets:

Coupling currents from step 2
determined from a linear superposition
Experiment
Typical small RC interconnect
structure
Rise time of 200 ps or 100 ps
Power supply voltage of 1.8 V
Conventional circuit simulation vs.
proposed metric
Run-time comparisons for various
circuit sizes
Accuracy Results
Node Circuit Simulation Proposed Metric
1
0.0084
0.0084
2
0.016
0.016
3
0.0227
0.0227
4
0.0286
0.0286
5
0.0336
0.0336
6
0.0378
0.0379
7
0.0412
0.0412
8
0.0437
0.0438
9
0.0454
0.0454
10
0.0462
0.0463
% Error
0.00%
0.00%
0.00%
0.00%
0.00%
0.26%
0.00%
0.23%
0.00%
0.22%
10 nodes, 200 ps rise time
Accuracy Results
Node Circuit Simulation Proposed Metric
1
0.0147
0.0168
2
0.0277
0.0319
3
0.0392
0.0454
4
0.0492
0.0572
5
0.0578
0.0673
6
0.0651
0.0757
7
0.0709
0.0824
8
0.0752
0.0875
9
0.0782
0.0908
10
0.0797
0.0925
% Error
7.73%
13.10%
13.65%
13.98%
14.11%
14.00%
13.95%
14.05%
13.87%
13.83%
10 nodes, 100 ps rise time
Accuracy Results
Metric accuracy degrades with reduction
in rise times
Metric estimation is more conservative
than circuit models
Fast rise times dont allow circuit to reach
ramp steady state noise
Loading of interconnect normally does not

allow for very small rise times
Metric accuracy should be acceptable for
many applications
Run-time Results
Circuit
Number
Number of
Elements
1
2
3
4
500
5,000
50,000
500,000
Arnoldi Model Proposed

Reduction Metric (Matrix
Method)
.2s
5.86s
145s
-
.00s
.07s
3.44s
360.55s
Proposed
Metric (By
Inspection)
.00s
.01s
.05s
.35s
Arnoldi-based model reduction used a

matrix solution to compute circuit response
Requires repeated factorizations, eigenvalue
calculations, and time exponential evaluations
Conclusions
The proposed metric determines an
upper bound on coupled noise for RC
and over-damped RLC interconnects
Metric becomes less accurate as rise
time decreases
The proposed metric is much more

run-time efficient than circuit
modeling methods
Improved Crosstalk Modeling for Noise

Constrained Interconnect Optimization
Jason Cong, David Zhigang Pan &
Prasanna V. Srinivas
Department of Computer Science, UCLA
Magma Design Automation, Inc.
2 Results Way, Cupertino, CA 95014
MEMS Research Laboratory
Joe Zendejas and Jack W. Judy
Motivation
Deep sub-micron net designs have higher
aspect ratio (h/w)
Increased coupling capacitance between nets
Longer propagation delay
Increased logic errors --- Noise
Reduced noise margins

Lower supply voltages
Dynamic Logic
Crosstalk cannot be ignored

Aggressor / Victim Network

Aggressor
Victim
Assuming idle victim net

Ls: Interconnect length before coupling
Lc: Interconnect length of coupling
Le: Interconnect length after coupling
Aggressor has clock slew tr
2- Model
Victim net is modeled as 2 -RC circuits
Rd: Victim drive resistance
Cx is assumed to be in middle of Lc
Rise time
victim / aggressor
coupling capacitance
2- Model Parameters
Aggressor
Victim
Cs
C1
2
Cs Ce
C2
2
CL
Ce
Cl
2
Analytical Solution
Analytical Solution part 2

s-domain output voltage
Transform function H(s)
Analytical Solution part 3

Aggressor input signal
Output voltage
Simplification of Closed Form Solution

Closed form solution complicated
Non-intuitive
Noise peak amplitude, noise width?
Dominant-pole simplification
Dominant-Pole Simplification
RC delay from upstream resistance of coupling element
Elmore delay of victim net
Intuition of Dominant Pole Simplification
vout rises until tr and

decays after
vmax evaluated at tr
Extension to RC Trees
Similar to previous model with addition of

lumped capacitances
Results
Average errors of 4%
95% of nets have errors less than 10%
Spice Comparison
peak noise
noise width
Effect of Aggressor Location

As aggressor is moved close to receiver,
peak noise is increased
Ls varies from 0 to 1mm
Lc has length of 1mm
Le varies from 1mm to 0
Optimization Rules
Rule 1:
If RsC1 < ReCL
Sizing up victim driver will reduce peak
noise
If RsC1 > ReCL and tr << tv

Driver sizing will not reduce peak noise
Rule 2:
Noise-sensitive victims should avoid
near-receiver coupling
Optimization Rules part 2

Rule 3:
Preferred position for shield insertion is near a
noise sensitive receiver
Rule 4:
Wire spacing is an effective way to reduce
noise
Rule 5:
Noise amplitude-width product has lower
bound
And upper bound
Conclusions
2- model achieves results within 6%
error of HSPICE simulation
Dominant node simplification gives
intuition to important parameters
Design rules established to reduce
noise
References
Anirudh Devgan, Efficient Coupled Noise
Estimation for On-chip Interconnects, ICCAD,
1997.
J. Cong, Z. Pan and P. V. Srinivas, Improved
Crosstalk Modeling for Noise Constrained
Interconnect Optimization, Proc. Asia South
Pacific Design Automation Conference
(ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico
Yokohama, Japan.

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EE 201A

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Efficient Coupled Noise Estimation

MEMS Research Laboratory

Joe Zendejas and Jack W. Judy

Circuit or timing simulation (like SPICE) can

Inefficient for noise verification and avoidance

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Maximum Induced Noise

Assume Vs is a finite or infinite ramp

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Maximum Induced Noise

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Requires circuit analysis of the

Requires a matrix multiplication

Requires circuit analysis of the victim

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Aggressor circuit transformation:

Replace input source with its derivative

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Convert steady state derivative on the

i : index of node on the victim net

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Replace capacitors with coupling currents

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Multiple aggressor nets:

Jeff Wong and Dan Vasquez

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

10 nodes, 200 ps rise time

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

10 nodes, 100 ps rise time

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez

Loading of interconnect normally does not

EE 201A Modeling and Optimization for VLSI Layout

Jeff Wong and Dan Vasquez