Professional Documents
Culture Documents
Discussion D4.5
Operation
HEX
Start
Hundreds
Tens
Units
Binary
F
1 1 1 1
F
1 1 1 1
Hundreds
1
1
1 0
2
Tens
1
0
0
0
1
1 1
0 0
0 1
0 1
1 0
5
Units
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
1
1 1
0 1
1 0
0 0
0 0
0 1
0 1
1 1
0 1
1 0
5
Binary
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
F
1 1 1 1
1 1 1
1 1
1
1
Tens
Units
1
1
1
1 1
1 1 1
0 1 1
0 1 0
4
Binary
1
1
1
0
0
0
E
1 1 1 0
1 1 0
1 0
0
C
S3 S2 S1 S0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S3
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
S2
0
0
0
0
1
0
0
0
0
1
X
X
X
X
X
X
S1
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
S0
0
1
0
1
0
0
1
0
1
0
X
X
X
X
X
X
K-Map for S3
A1 A0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S3
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
S2
0
0
0
0
1
0
0
0
0
1
X
X
X
X
X
X
S1
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
S0
0
1
0
1
0
0
1
0
1
0
X
X
X
X
X
X
A3 A2
00
01
11
10
00
01
11
10
S3 = A3
+ A2 * A0
+ A2 * A1
Binary-to-BCD
Converter
C1
C2
C3
C6
C4
C7
C5
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
hunds
tens
BCD output
units
Hex FF
8-bit binary input
0 B7 B6 B5 B4 B3 B2 B1 B0
1
Binary-to-BCD
Converter
C1
1
C2
RTL Solution
C3
0
1
C6
1
C4
0
C7
1
C5
1
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
hunds
tens
units
BCD output
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
Tens
Units
Binary
5 4 3 2 1 0
3
1 1 1 1 1 1
1
1 1
1 1 1 1 1
1 1 1 1
1 1 1
1 1 1
1 0 1 0
1 1 1
0 1 0 1
1 1
1 0 0 0
1 1
1 1
0 0 0 1
1 1 0
0 0 1 1
13
10 9
0
6 5
Operation
binbcd6.vhd
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
entity binbcd6 is
port (
B: in STD_LOGIC_VECTOR (5 downto 0);
P: out STD_LOGIC_VECTOR (6 downto 0)
);
end binbcd6;
architecture binbcd6_arch of binbcd6 is
begin
bcd1: process(B)
variable z: STD_LOGIC_VECTOR (12 downto 0);
Tens
Units
Binary
5 4 3 2 1 0
3
1 1 1 1 1 1
1
1 1
1 1 1 1 1
1 1 1 1
1 1 1
1 1 1
1 0 1 0
1 1 1
0 1 0 1
1 1
1 0 0 0
1 1
1 1
0 0 0 1
1 1 0
0 0 1 1
13
10 9
0
6 5
Operation
binbcd6.vhd (cont.)
begin
for i in 0 to 12 loop
z(i) := '0';
end loop;
z(8 downto 3) := B;
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
Tens
Binary
5 4 3 2 1 0
3
1 1 1 1 1 1
1
1 1
1 1 1 1 1
1 1 1 1
1 1 1
1 1 1
1 0 1 0
1 1 1
0 1 0 1
1 1
1 0 0 0
1 1
1 1
0 0 0 1
1 1 0
0 0 1 1
13
10 9
for i in 0 to 2 loop
if z(9 downto 6) > 4 then
z(9 downto 6) := z(9 downto 6) + 3;
end if;
z(12 downto 1) := z(11 downto 0);
end loop;
P <= z(12 downto 6);
end process bcd1;
end binbcd6_arch;
Units
0
6 5
binbcd6.vhd
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
Tens
Units
Binary
5 4 3 2 1 0
3
1 1 1 1 1 1
1
1 1
1 1 1 1 1
1 1 1 1
1 1 1
1 1 1
1 0 1 0
1 1 1
0 1 0 1
1 1
1 0 0 0
1 1
1 1
0 0 0 1
1 1 0
0 0 1 1
13
10 9
0
6 5
binbcd8.vhd
entity binbcd is
port (
B: in STD_LOGIC_VECTOR (7 downto 0);
P: out STD_LOGIC_VECTOR (9 downto 0)
);
end binbcd;
binbcd8.vhd (cont.)
Hundreds
Tens
Units
Binary
4
3
1
1
1 0
2
9 8
17 16
1
0
0
0
7
15
1
0
0
0
1
1
1
0
1
1
0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
12
3
11
1
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
5
1
1
1
0
1
0
1
1
1
1
0
1
0
8
1
1
1
1
1
1
1
1
1
1
1
1
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
for i in 0 to 4 loop
if z(11 downto 8) > 4 then
z(11 downto 8) := z(11 downto 8) + 3;
end if;
if z(15 downto 12) > 4 then
z(15 downto 12) := z(15 downto 12) + 3;
end if;
z(17 downto 1) := z(16 downto 0);
end loop;
P <= z(17 downto 8);
end process bcd1;
end binbcd_arch;
F
1 1 1 1
1 1 1
1 1
1
1
Hex FF
8-bit binary input
binbcd8.vhd
0 B7 B6 B5 B4 B3 B2 B1 B0
1
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
Add 3
Shift 7
Add 3
Shift 8
BCD
P
z
Hundreds
Tens
Units
Binary
4
3
1
1
1 0
2
9 8
17 16
1
0
0
0
7
15
1
1 1
0 0
0 1
0 1
1 0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
12
3
11
1
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
5
1
1
1
0
1
0
1
1
1
1
0
1
0
8
1
1
1
1
1
1
1
1
1
1
1
1
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
F
1 1 1 1
1 1 1
1 1
1
1
C1
1
C2
1
C3
0
1
C6
1
C4
0
C7
1
C5
1
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
hunds
tens
units
BCD output
B7
B6
B5
B4
B3
B2
B1 B0
C1
16-bit
Binary-to-BCD
Converter
C2
C3
C14
C4
C15
C5
C16
C24
C6
C17
C25
C18
C26
C31
C7
C19
C27
C32
C8
C20
C28
C33
C9
C21
C29
C34
thousands
C11
C22
C30
P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9
ten thousands
C10
C12
C23
P8
hundreds
BCD output
P7
C13
P6
P5
tens
P4
P3
P2
P1 P0
units
B6
B5
B4
B3
B2
B1 B0
C1
binbcd16.vhd
C2
C3
C14
C4
C15
C5
C16
C24
C6
C17
C25
C31
C7
C18
C26
entity binbcd16 is
port (
B: in STD_LOGIC_VECTOR (15 downto 0);
P: out STD_LOGIC_VECTOR (18 downto 0)
);
end binbcd16;
B7
C19
C27
C32
C8
C20
C28
C33
C9
C21
C29
C34
C10
C22
C30
P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8
ten thousands
thousands
C11
hundreds
BCD output
C12
C23
P7
C13
P6
P5
tens
P4
P3
P2
P1 P0
units
begin
for i in 0 to 34 loop
z(i) := '0';
end loop;
z(18 downto 3) := B;
binbcd16.vhd (cont.)
B7
B6
B5
B4
B3
B2
B1 B0
C1
C2
C3
C14
C4
C15
C16
for i in 0 to 12 loop
if z(19 downto 16) > 4 then
z(19 downto 16) := z(19 downto 16) + 3;
end if;
if z(23 downto 20) > 4 then
z(23 downto 20) := z(23 downto 20) + 3;
end if;
if z(27 downto 24) > 4 then
z(27 downto 24) := z(27 downto 24) + 3;
end if;
if z(31 downto 28) > 4 then
z(31 downto 28) := z(31 downto 28) + 3;
end if;
z(34 downto 1) := z(33 downto 0);
end loop;
P <= z(34 downto 16);
end process bcd1;
end binbcd16_arch;
C5
C24
C6
C17
C25
C18
C26
C31
C7
C19
C27
C32
C8
C20
C28
C33
C9
C21
C29
C34
thousands
C11
C22
C30
P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9
ten thousands
C10
C12
C23
P8
hundreds
BCD output
P7
C13
P6
P5
tens
P4
P3
P2
P1 P0
units
B7
B6
B5
B4
B3
B2
B1 B0
C1
binbcd16.vhd
C2
C3
C14
C4
C15
C5
C16
C24
C6
C17
C25
C18
C26
C31
C7
C19
C27
C32
C8
C20
C28
C33
C9
C21
C29
C34
thousands
C11
C22
C30
P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9
ten thousands
C10
C12
C23
P8
hundreds
BCD output
P7
C13
P6
P5
tens
P4
P3
P2
P1 P0
units