Professional Documents
Culture Documents
Sequential Logic/
Circuits
Sequential vs
Combinational
Output of any combinational logic circuit
depends directly on the input.
Generally, in a sequential logic circuit, the
output is dependent not only on the input but
also on the stored state.
Latch is used for the temporary storage of a data
bit
FF form the basis for most types of sequential
logic, such as registers and counters. Also, two
types of timing circuits; (1)one-shot and (2) 555
timer
Sequential vs
Combinational circuits.
Combinational
Output determined solely by inputs.
Can draw solely with left-to-right signal paths.
input
Comb. Cct.
output
Sequential circuits.
Output determined by inputs XXX previous
outputs.
Feedback loop.
input
Seq. Cct.
output
Introduction
Latches and FFs are the basic single-bit memory
Introduction
Latches:
D, S-R Latch
Gate S-R Latch
Gate D-Latch
FFs:
Similar to latch
Edge-Triggered Flip-Flop (S-R, J-K, D)
except that it
Asynchronous Inputs
can change
Master-Slave Flip-Flop
state only on
Flip-Flop Operating Characteristics
the occurrence
Flip-Flop Applications:
of one edge of
One-shots & The 555 Timer
a clock pulse.
Latches
Type of temporary storage device that has
Waveforms
Hold
Hold
Hold
hold
hold
set
reset
not allowed
Clock signal
0
Rising edges of
the clock
(Positive-edge
triggered)
Falling edges
of the clock
(Negative-edge
triggered)
Clock Cycle
Time
Example:
CLK/C
Q_________________
SET (stores a 1)
RESET (stores a 0)
Example:
CLK
Q0
Q0
Hold
Reset
Set
Q0
Q0
CLK
Q0
Q0
Hold
Reset
Set
Q0
Q0
Flip-Flop Applications
Parallel Data Storage
Frequency Division
Counting
Flip-flop Characteristics
Propagation delay time is specified for the rising and falling outputs. It is
measured between the 50% level of the clock to the 50% level of the
output transition.
50% point on triggering edge
CLK
CLK
tPLH
50% point
Q
tPHL
Flip-flop Characteristics
Another propagation delay time specification is the time required for an
asynchronous input to cause a change in the output. Again it is measured
from the 50% levels. The 74AHC family has specified delay times under 5
ns.
PRE
50% point
50%
point
Q
tPLH
CLR
50% point
50% point
Q
tPHL
Flip-flop Characteristics
Set-up time and hold time are times required before and after the clock
transition that data must be present to be reliably clocked into the flip-flop.
D
CLK
Set-up time, ts
D
CLK
Hold time, tH
tw = 1.1R1C1 = 1.1(2000)(1F) =
2.2ms
One-Shots
The one-shot or monostable multivibrator is a device with only
one stable state. When triggered, it goes to its unstable state for a
predetermined length of time, then returns to its stable state.
+V
Q
tW
REXT
CEXT
CX
Trigger
RX/CX
1.44
R1 2 R2 C1
(4)
R1
(7)
R2
C1
RESE
T
DISCH
(8)
VCC
(6)
(3)
THRE
OUT
S
(2)
(5)
TRIG CONT
GND
(1)
100
C1 (F)
10
(7)
1.0
R2
0.1
0.01
0.001
0.1
(4)
R1
C1
RESE
T
DISCH
(8)
VCC
(6)
(3)
THRE
OUT
S
(2)
(5)
TRIG CONT
GND
(1)
1.0
10
100
f (Hz)
1.0k
10k
100k
tH = .7 (R1+R2)C1 =2.1ms
0.7mst
t
H = time output high
tL = .7R2C1 =