Microcontrollers

 Specially designed microprocessors

– It is small on chip computer
 Highly integrated chip
includes all or most parts needed for controller
 A typical microcontroller has:
– bit manipulation
– easy and direct access to I/O
– quick and efficient interrupt processing
 Microcontroller drastically reduces design cost

1/175
Worldwide Microcontroller shipments
- in millions of dollars -

'95 '96 '97 '98 '99 00

4-bit 1826 1849 1881 1856 1816 1757
8-bit 5634 6553 7529 8423 9219 9715
16-bit 1170 1628 2191 2969 3678 4405

2/175
Worldwide Microcontroller shipments
- in millions -

'95 '96 '97 '98 '99 00

4-bit 1100 1100 1096 1064 1025 970
8-bit 1803 2123 2374 2556 2681 2700
16-bit 157 227 313 419 501 585

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Applications
 Appliances
(microwave oven, refrigerators, television and VCRs, stereos)
 Computers and computer equipment
(laser printers, modems, disk drives)
 Automobiles
(engine control, diagnostics, climate control),
 Environmental control
(greenhouse, factory, home)
 Instrumentation
 Aerospace
 Robotics, etc...

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Flavors
 4, 8, 16, or 32 bit microcontrollers
 specialized processors include features specific for
– communications,
– keyboard handling,
– signal processing,
– video processing, and other tasks.

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 Part 1

Popular Microcontrollers
 8048 (Intel)
 8051 (Intel and others)
 80c196 (MCS-96)
 80186,80188 (Intel)
 80386 EX (Intel)
 65C02/W65C816S/W65C134S (Western Design Center)
 MC14500 (Motorola)

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 Part 2

Popular Microcontrollers
 68HC05 (Motorola)
 68HC11 (Motorola and Toshiba)
 683xx (Motorola)
 PIC (MicroChip)
 COP400 Family (National Semiconductor)
 COP800 Family (National Semiconductor)
 HPC Family (National Semiconductor)
 Project Piranha (National Semiconductor)

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 Part 3

Popular Microcontrollers
 Z8 (Zilog)
 HD64180 (Hitachi)
 TMS370 (Texas Instruments)
 1802 (RCA)
 MuP21 (Forth chip)
 F21 (Next generation Forth chip)

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 Part 1

Programming Languages
 Machine/Assembly language
 Interpreters
 Compilers
 Fuzzy Logic and Neural Networks

9/175
 Part 1

Development Tools
 Simulators
 Resident Debuggers
 Emulators
 Java on Embedded Systems

10/175
Choosing microcontoller
 Technical support
 Development tools
 Documentation
 Purchasing more devices at one manufacturer
(A/D, memory, etc.)
 Additional features
(EEPROM, FLASH, LCD driver, etc.)

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Microcontrollers
 Basic parts are: e x te rn a l
in e r r u p ts
– Central Processing Unit
– RAM
in te r r u p t ROM tim e r 1 c o u n te r
– EPROM/PROM/ROM or c o n tro l
RAM
tim e r 0 in p u ts
FLASH Memory
– I/O serial or/and parallel
– timers CPU

– interrupt controller
 Optional parts are: O SC
bus 4 I/O s e ria l
c o n tro l p o rts p o rt
– Watch Dog Timer
– AD Converter
TxD RxD
– LCD driver P0 P2 P1 P3
a d d re s s /
– etc. d a ta

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Intel 8051
 A typical 8051 contains: RAR
128x8
RAM
4K x8
ROM
PCH

PCL
DPH

DPL
P2 LATCH

PORT2

– CPU with Boolean processor RAM SENSE

P0 LATC H

BUFFER AM PS

– 5 or 6 interrupts:

INTERNAL BUS
P2 LATCH

2 external, 2 priority levels PORT2

ALU
A IR
ROM

– 2 or 3 16-bit timer/counters TM P2 TM P1 B
PLA

– programmable full-duplex PSW SP

CONTROL

serial port ALU

– 32 I/O lines (four 8-bit ports) P0 LATCH SCON TCON IE P3 LATCH

– RAM
PORT0 S B U F (R E C ) TM OD IP PORT3

S B U F (X M IT ) TL0 IN T E R R U P T
CONTROL
S E R IA L TH0

– ROM/EPROM in some models PORT

TL1

TH1

T IM E R
CONTROL

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 Part 1

Intel 8051: Pin Description

VCC VSS
 VSS - Ground: 0V XTAL1
 VCC - Power Supply

PORT 0
ADDRESS AND
 P0.0-P0.7 - Port 0 DATA BUS
XTAL2
– Open drain,
RST
bi-directional I/O port

PORT 1
E A /V p p
– Pins that have 1s written to PSEN
A L E /P R O G
them float and can be used

SECONDARY FUNCTIONS
RxD
as high-impedance inputs TxD

PORT 2
PORT 3
– Multiplexed low-order IN T 0
ADDRESS BUS
IN T 1
address and data bus during T0
accesses to external program T1
W R
and data memory
RD

14/175

Intel 8051: Pin Description
 P2.0-P2.7 - Port 2
– Bi-directional I/O port
with internal pull-ups
– Pins that have 1s written to
them float and can be used as
high-impedance inputs.
– Port 2 emits high-order address
byte during accesses to
external program and data
memory
 P3.0-P3.7 - Port 3
– Bi-directional I/O port
with internal pull-ups
– Pins that have 1s written to
them float and can be used as
high-impedance inputs.
Part 2
 Port 3 serves the
special features:
– RxD - Serial input port
– TxD - Serial output port
– INT0 - External interrupt
– INT1 - External interrupt
– T0 - Timer 0 external input
– T1 - Timer 1 external input
– WR - External data memory
write strobe
– RD - External data memory
read strobe
15/175

Intel 8051: Pin Description
 RST - Reset
– A high on this pin
for two machine cycles resets
the devices
 ALE - Address Latch Enable
– Output pulse for latching
the low byte of address
during an access to external
memory
 PSEN - Program Store Enable
– Read strobe to external
program memory
Part 3
 EA - External Access Enable
– EA must be externally held
low to enable device to fetch
code from external memory
locations.
 XTAL1 - Crystal 1
– Input to the inverting
oscillator amplifier and
input to internal clock
generator circuits
 XTAL2 - Crystal 2
– Output from the inverting
oscillator amplifier
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 Part 1

Intel 8051: Pin Configurations

P 1 .0 1 40 Vcc
P 1 .1 2 39 P 0 .0 /A D 0
 Dual In-Line Package
P 1 .2 3 38 P 0 .1 /A D 1
 Plastic Lead Chip Carrier P 1 .3 4 37 P 0 .2 /A D 2
 Plastic Quad Flat Pack P 1 .4 5 36 P 0 .3 /A D 3
P 1 .5 6 35 P 0 .4 /A D 4
P 1 .6 7 34 P 0 .5 /A D 5
P 1 .7 8 33 P 0 .6 /A D 6
RST 9 32 P 0 .6 /A D 6
R x D /P 3 .0 10 31 EA
TxD/ 11 30 ALE
P 3 .1
IN T 0 /P 3 .2 12 29 PSEN
IN T 1 /P 3 .3 13 28 P 2 .7 /A 1 5
T 0 /P 3 .4 14 27 P 2 .6 /A 1 4
T 1 /P 3 .5 15 26 P 2 .5 /A 1 3
W R /P 3 .6 16 25 P 2 .4 /A 1 2
R D /P 3 .7 17 24 P 2 .3 /A 1 1
XTAL2 18 23 P 2 .2 /A 1 0
XTAL1 19 22 P 2 .1 /A 9
Vss 20 21 P 2 .0 /A 8
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 Part 2

Intel 8051: Pin Configurations

–6 –1 –40 44 34

–7 –39 1 33

PQFP PLCC

11 23
–17 –29

–18 –28
12 22
–1 NIC –16 P3.4/T0 –31 P2.7/A15
1 P1.5 16 VSS 31 P0.6/AD6
–2 P1.0 –17 P3.5/T1 –32 PSEN
2 P1.6 17 NIC 32 P0.5/AD5
–3 P1.1 –18 P3.6/WR –33 ALE
3 P1.7 18 P2.0/A8 33 P0.4/AD4
–4 P1.2 –19 P3.4/RD –34 NIC
4 RST 19 P2.1/A9 34 P0.3/AD3
–5 P1.3 –20 XTAL2 –35 EA
5 P3.0/RxD 20 P2.2/A10 35 P0.2/AD2
–6 P1.4 –21 XTAL1 –36 P0.7/AD7
6 NIC 21 P2.3/A11 36 P0.1/AD1
–7 P1.5 –22 VSS –37 P0.6/AD6
7 P3.1/TxD 22 P2.4/A12 37 P0.0/AD0
–8 P1.6 –23 NIC –38 P0.5/AD5
8 P3.2/INT0 23 P2.5/A13 38 VCC
–9 P1.7 –24 P2.0/A8 –39 P0.4/AD4
9 P3.3/INT1 24 P2.6/A14 39 NIC
–10 RST –25 P2.1/A9 –40 P0.3/AD3
10 P3.4/T0 25 P2.7/A15 40 P1.0
–11 P3.0/RxD –26 P2.2/A10 –41 P0.2/AD2
11 P3.5/T1 26 PSEN 41 P1.1
–12 NIC –27 P2.3/A11 –42 P0.1/AD1
12 P3.6/WR 27 ALE 42 P1.2
–13 P3.1/TxD –28 P2.4/A12 –43 P0.0/AD0
13 P3.4/RD 28 NIC 43 P1.3
–14 P3.2/INT0 –29 P2.5/A13 –44 VCC
14 XTAL2 29 EA 44 P1.4
–15 P3.3/INT1 –30 P2.6/A14
15 XTAL1 30 P0.7/AD7 18/175
 Part 1

Intel 8051: CPU

 Primary elements are: RAR
128x8
RAM
4K x8
ROM
PCH

PCL
DPH

DPL
P2 LATCH

PORT2

– eight bit ALU P0 LATCH

with associated registers RAM

BUFFER
SENSE
AM PS

A, B, PSW and SP

INTERNAL BUS
P2 LATCH

– sixteen-bit PORT2
ALU
Program Counter (PC) A
ROM
IR

PLA

– Data Pointer registers TM P2 TM P1 B

CONTROL
PSW SP
ALU

P0 LATCH SCON TCON IE P3 LATCH

PORT0 S B U F (R E C ) TM OD IP PORT3

S B U F (X M IT ) TL0 IN T E R R U P T
CONTROL
S E R IA L TH0
PORT
TL1

TH1

T IM E R
CONTROL

19/175
 Part 2

Intel 8051: CPU

 The ALU can manipulate one-bit as well as eight-bit data types
– This features makes the 8051 especially well suited
for controller-type applications
 A total of 51 separated operations
move and manipulate three data types:
– Boolean (1-bit)
– Byte (8-bit)
– Address (16-bit)

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 Part 3

Intel 8051: CPU

 Instruction types:
– Arithmetic Operations
– Logic Operations for Byte Variables
– Data Transfer Instructions
– Boolean Variable Manipulation
– Program Branching and Machine Control

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 Part 4

Intel 8051: CPU

 There are eleven addressing modes:
– seven for data
– four for program sequence control
 Most operations allow several addressing modes,
bringing total number of instructions to 111,
encompassing 255 of the 256 possible 8-bit instruction opcodes
 8051 instruction set fares well at both
real-time control and data intensive algorithms

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 Part 1

Intel 8051: Memory Organization

 Program memory is separate distinct from data memory
– Each memory type has a different addressing mechanism,
different control signals, and a different functions
 Architecture supports several distinct “physical” address spaces
functionally separated at the hardware level:
– On - chip program memory
– On - chip data memory
– Off - chip program memory
– Off - chip data memory
– On chip special function registers

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 Part 2

Intel 8051: Memory Organization

 Program (Code) memory
– Holds the actual 8051 program that is to be run

– Limited to 64K
– may be found on-chip as ROM or EPROM
– may be stored completely off-chip in
an external ROM or an external EPROM
– Flash RAM is also another popular method of storing a program
– Various combinations of these memory types may be used
(e.g. 4 K on-chip and 64 KB off-chip)

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 Part 3

Intel 8051: Memory Organization

 External RAM
– External RAM is any random access memory which is found off-chip
– External RAM is slower
• To increment an Internal RAM location by 1
requires only 1 instruction and 1 instruction cycle
• To increment a 1-byte value stored in External RAM
requires 4 instructions and 7 instruction cycles
– While Internal RAM is limited to 128 bytes (256 bytes with an 8052),
the 8051 supports External RAM up to 64K

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 Part 4

Intel 8051: Memory Organization

 On-chip memory
– Two types:
• Internal RAM; and
• Special Function Register (SFR) memory
– Internal RAM is on-chip so it is the fastest RAM available
– Internal RAM is volatile, when the 8051 is reset this memory is cleared
– Special Function Registers (SFRs) are areas of memory that
control specific functionality of the 8051 processor

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 Part 1

Intel 8051: Memory Access

 PORT 2 : High byte of address EA
PORT2 A 8 -A 1 5 A 8 -A 1 5 A 8 -A 1 5
held for the duration of
read or write cycle PORT0 A D 0 -A D 7 A 0 -A 7 A 0 -A 7 A 0 -A 7

Static RAM

ROM
LATCH
CS
 PORT 0 : time multiplexed "0"
RD "0" CS
ALE LE W R OE

low byte of address with data byte 8051

D 0 -D 7
 Signal ALE: used to capture the
address byte into an external latch
PSEN
RD
W R

6 4 K b y te s - P r o g r a m m e m o r y (e x te r n a l)
6 4 K b y te s - D a ta M e m o ry

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 Part 2

Intel 8051: Memory Access

STAG E 1 STAGE 2 STAGE 3 STAG E 4 STAG E 5 STAG E 6 STAG E 4 STAGE 5 STAGE 6 STAG E 1 STAG E 2 STAG E 3
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

XTAL1 XTAL1

ALE ALE

PSEN RD

IN S . IN S . IN S . FLOAT d a ta FLOAT
A 0 -A 7 A 0 -A 7 A 0 -A 7
P0 IN IN IN P 0 in

A 8 -A 1 5 A 8 -A 1 5 A 8 -A 1 5 A 8 -A 1 5
P2 P2

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 Part 1

Intel 8051: Program Memory

PRO GRAM M EM O RY
 Up to 64K of Program Memory 0xFFFF
 PSEN: read strobe
for all external program fetches

EXTERNAL
 PSEN: not activated for
internal program fetches
 Depending on EA pin
lowest bytes can be either
in the on-chip ROM or in an external ROM

EA = 0 EA = 1

0x0000

PSEN

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 Part 2

Intel 8051: Program Memory

 Boot address - 0x0000
 Each interrupt is assigned LO W ER PART O F PRO G RAM M EM O RY
a fixed location in Program Memory
 If interrupt is not going to used,
0x0028
its service location is available as
general purpose Program Memory 0x0023

0x0018
IN T E R R P U T
L O C A T IO N S
0x0013
8 BYTES
0x0008

0x0003

RESET 0x0000

30/175
 Part 3

Intel 8051: Program Memory

 Port 0 and Port 2 are dedicated PORT0 IN S T R
to bus functions during
external Program Memory fetches EA
A D 0 -A D 7 A 0 -A 7

LATCH
ADDR
ALE LE

PORT2 A 8 -A 1 5

PSEN OE

8051 EROM

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 Part 1

Intel 8051: Data Memory

DATA M EM ORY

 Up to 64K Data Memory 0xFFFF

 Access to Data memory use

RD or WR to strobe the memory

EXTERNAL
IN T E R N A L

0xFF

0x00 0x0000

RD W R

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 Part 2

Intel 8051: Data Memory

 Internal Memory Addresses INTERNAL
are one byte wide - 0xFF

128 bytes address space

(256 - Intel 8052) ACCESSIBLE ACCESSIBLE
UPPER BY INDIRECT BY DIRECT
 Direct addressing higher then 0x7F 128 ADDRESSING ADDRESSING
access one memory space, ONLY ONLY

indirect addressing higher then 0x7F

access a different memory space 0x7F

 Upper 128 and SFR space SPECIAL

PORTS
FUNCTION
STATUS BITS
occupying same block of addresses, ACCESSIBLE REGISTERS
CONTOL BITS
LOWER BY DIRECT
although they are 128 AND INDIRECT
TIMER REGISTERS
STACK POINTER
physically separate entities ADDRESSING
ACCUMULATOR
(ETC.)

0x00

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 Part 3

Intel 8051: Data Memory

 The lowest 32 bytes are grouped
into 4 banks of 8 registers LOWER 128 BYTES OF
INTERNAL RAM
 Program instructions call out 0x7F

these registers R0 through R7

 Two bits in the PSW
0x2F
selects register bank BANK SELECT BITS BIT ADDRESSABLE SPACE
IN PSW (BIT ADDRESSES 0-7F)
– Register instructions are shorter
0x20
 The next 16 bytes form a 11
0x1F

block of bit-addressable space 0x18

0x17 4 BANKS OF
10 8 REGISTERS
0x10 R0-R7
0x0F
01
0x08
0x07 RESET VALUE OF
00 STACK POINTER
0x00

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 Part 1

Intel 8051: SFR

 SFRs are accessed as if they were normal Internal RAM
 SFR registers exist in the address range of 80h through FFh
 Each SFR has an address and a name

35/175
 Part 2

Intel 8051: SFR

0 1 2 3 4 5 6 7
F8 FF
F0 B F7
E8 EF
E0 ACC E7
D8 DF
D0 PSW D7
C8 CF
C0 C7
B8 IP BF
B0 P3 B7
A8 IE AF
A0 P2 A7
98 SCON SBUF 9F
90 T1 97
88 TCON TMOD TL0 TL1 TH0 TH1 8F
80 T0 SP DPL DPH PCON 87

36/175

Intel 8051: SFR
 Accumulator (A)
– Accumulator register
 B Register (B)
– Used during multiply and
divide operations
 PSW
– Contains program status
information
 Stack Pointer (SP)
– Eight bits wide
– Stack may reside anywhere
in on chip RAM
Part 3
– The Stack Pointer is
initialized on 0x07
after a reset, and this causes
stack to begin at location
0x08
 Data Pointer(DPTR)
– Consist high byte (DPH) and
low byte (DPL)
– It may be manipulated as a
16-bit register or as two
independent 8-bit registers
37/175

Intel 8051: SFR
 Ports 0 to 3 (P0, P1, P2, P4)
– Latches of Port 0 to 3,
respectively
 Serial Data Buffer (SDBF)
– It is actually two separated
registers: receive and
transmit buffer registers
– When data is moved to SBUF
it goes to the transmit buffer
– When data is moved from
SBUF it comes from the
receive buffer
Part 4
 Timer Registers (T1, T0)
– (TH1, TL1) (TH0, TL0)
Counting Registers for
Timer/Counter 1 and 0
 Control Registers
– IP: Interrupt priority
– IE: Interrupt enable
– TMOD Timer/Counter mode
– TCON Timer/Counter control
– PCON Power control
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Intel 8051: PSW
7 6 5 4 3 2 1 0
PSW CY AC F0 RS1 RS0 OV - P

Carry flag Parity flag

Auxiliary Carry flag Overflow flag
Flag 0 Registar Bank
Registar Bank Select bit 1
Select bit 1

 Auxiliary Carry flag is used for BCD operations

 Flag 0 is available to user for general purposes
 The contest of (RS1, RS2) enable working register banks as follows:
00 - Bank 0 [0x00-0x07], 01 - Bank 1 [0x08-0x0f],
10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]

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 Intel 8051: CPU Timing
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

ALE

 The internal clock generator defines

the sequence of states that make up a machine cycle
 A machine cycle consists of 6 states, numbered S1 through S6
 Each state time lasts for two oscillator periods
 Each state is then divided into a Phase 1 and Phase 2 half

40/175
 Part 1

Intel 8051: Port Structures

 Pseudo bi-directional +5V +5V
READ/MODIFY/
I/O port structure WRITE

– On Port0 R2 is disabled ENB

except during bus operations Q2

(open-collector output)
 The address latch bit is updated by SET
R1 R2
INTERNAL BUS D Q I/O
direct addressing instructions WRITE PULSE
PIN

 The value read is “OR-tied” function Q

Q1
CLR

of Q1 and the external device BUS CYCLE

TIMING
 To use a pin for input
INPUT
latch must be set ENB BUFFER

READ

41/175
Intel 8051: Port Interfacing
 The output buffers of Ports 0, 1, 2 and 3
can each drive 4 LS TTL inputs
 Can be driven by open-collector and open-drain outputs
– 0-to-1 transitions will not be fast since
there is little current pulling the pin up
 Port 0 output buffers can each drive 8 LS TTL inputs
(external bus mode)
 As port pins PORT 0 requires external pull-ups
to be able to drive any inputs bit

42/175
Intel 8051: Special Peripheral Functions
 There are few special needs
common among control-oriented computer systems:
– keeping tracks of elapsed time
– maintaining a count of signal transitions
– measuring the precise width of input pulses
– communicating with other systems
– closely monitoring asynchronous external events

43/175
 Part 1

Intel 8051: Timers/Counters

 Two 16-bit Timer/Counter registers
 Timer: Register is incremented every machine cycle
(1 machine cycle = 12 oscillator periods)
 Counter: Register is incremented in response to
1-to-0 transition at its corresponding external input pin (T0, T1)
– External input is sampled at S5P2 of every machine cycle
– When the samples show high in one cycle and low in the next,
the count is incremented
– The new count value is appears in S3P1
of the following detection cycle
– Max count rate is 1/24 of oscillator frequency
 TMOD - Timer/Counter mode register
 TCON - Timer/Counter control register

44/175
 Part 2

Intel 8051: Timers/Counters

 GATE: Gating control when set
 C/T: Counter or Timer Selector G ATE
T IM E R 0
 M1 M0: C /T
– 00: 8-bit Timer/Counter with 5-bit prescaler
– 01: 16-bit Timer/Counter T IM E R 1 M 1
– 10: 8-bit auto reload Timer/Counter M 0
– 11: (Timer0)
TL0 is 8-bit Timer/Counter controlled by
Timer0 control bits
TH0 is 8-bit timer only controlled by Timer1
control bits
– 11: (Timer1) Timer/Counter is stopped

45/175
 Part 3

Intel 8051: Timers/Counters

7 6 5 4 3 2 1 0
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

 TF: Overflow flag

– Set by hardware on Timer/Counter overflow
– Cleared by hardware when processor vectors to interrupt routine
 TR: Run control bit
– Set/Cleared by software to turn Timer/Counter on/off
 IE: Interrupt Edge flag
– Set by hardware when external interrupt edge detected
– Cleared when interrupt processed
 IT: Interrupt Type control bit
– Set/Cleared by software to specify
falling edge/low level triggered external interrupts
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 Part 4

Intel 8051: Timers/Counters

O SC 1 /1 2

TL1 TH1
TF1 IN T E R R U P T
(5 b its ) (8 b its )

T 1 P IN

TR1
G ATE M O DE 0
IN T 1 P IN

47/175
 Part 5

Intel 8051: Timers/Counters

O SC 1 /1 2
C /T = 0
TL1 TH1
TF1 IN T E R R U P T
(8 b its ) (8 b its )

C /T = 1
T 1 P IN

TR1
G ATE M O DE 1
IN T 1 P IN

48/175
 Part 6

Intel 8051: Timers/Counters

O SC 1 /1 2

TL1
TF1 IN T E R R U P T
(8 b its )

T 1 P IN
RELO AD

TR1
G ATE TH1
(8 b its )
M O DE 2
IN T 1 P IN

49/175
 Part 7

Intel 8051: Timers/Counters

O SC 1 /1 2
C /T = 0
TL0
TF0 IN T E R R U P T
(8 b its )

C /T = 1
T 0 P IN

TR0
G ATE M O DE 3
IN T 0 P IN
TH0
1 /1 2 fo sc TF1 IN T E R R U P T
(8 b its )

TR1
50/175
 Part 1

Intel 8051: Serial Port Interface

 Full-duplex
 Serial port receive and transmit registers
are both accessed at Special Function Register SBUF
– Writing to SBUF loads the transmit register
– Reading from SBUF accesses a physically separated receive register
 Four modes of operation
– In all four modes transmission is initiated by
any instruction that uses SBUF as destination register
– Reception is initiated in Mode 0 by condition RI=0 and REN=1
In other modes by the incoming start bit if REN=1
 SCON - Serial Port Control Register

51/175
 Part 2

Intel 8051: Serial Port Interface

7 6 5 4 3 2 1 0
SCON SM0 SM1 SM0 REN TB8 RB8 TI RI

 SM0 SM1:
– 00: Mode 0, Shift register, fosc//12
– 01: Mode 1, 8-bit UART, variable
– 10: Mode 2, 9-bit UART, fosc//32 or fosc//64
– 11: Mode 3, 9-bit UART, variable
 SM2: Enables multiprocessor features in Mode 2 and Mode 3
– When the stop bit is received,
the interrupt will be activated only if RB8=1 (9th bit =1)
 REN: Enables serial reception
– Set/Clear by software

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 Part 3

Intel 8051: Serial Port Interface

7 6 5 4 3 2 1 0
SCON SM0 SM1 SM0 REN TB8 RB8 TI RI

 TB8: 9th data bit that will be transmitted in Mode2 and Mode3
– Set/Clear by software
 RB8: 9th data bit that was received in Mode2 and Mode3
In Mode 1, if SM2=0, is the stop bit that was received
 TI: Transmit interrupt flag
– Set by hardware. Must be cleared by software
 RI: Receive interrupt flag
– Set by hardware. Must be cleared by software

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 Part 4

Intel 8051: Serial Port Interface

 MODE 0:
– Serial data enters and exits through RXD
– TXD outputs shift clock
– 8 bits are transmitted/received: 8 data bits (LSB first)
– The baud rate is fixed at 1/12 oscillator frequency
 MODE 1:
– Serial data enters through RXD, exits through TXD
– 10 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), stop bit(1)
– On receive the stop bit goes into RB8 in SCON register
– The baud rate is variable

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 Part 5

Intel 8051: Serial Port Interface

 MODE 2:
– Serial data enters through RXD, exits through TXD
– 11 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1)
– On transmit, the 9th bit is TB8 in SCON register
– On receive, the 9th bit goes into RB8 in SCON register
– The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency
 MODE 3:
– Same as MODE 2 in all respects except baud rate
– The baud rate is variable

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 Part 6

Intel 8051: Serial Port Interface

 Mode 0 Baud Rate = Oscillator frequency/12
 Mode 2 Baud Rate =[(2SMOD)/64]*Oscillator frequency
– SMOD is bit in Special Function Register PCON
 Mode 1 and Mode3 baud rate is
determined by Timer 1 overflow rate
 Mode 1,3 Baud Rate =[(2SMOD)/32]* Timer 1 Overflow Rate
– Timer mode, auto-reload :
Timer Overflow Rate=Oscillator frequency/[12*(256-TH1)]

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 Part 7

Intel 8051: Serial Port Interface

Timer1
Baud
fosc SMOD
Rate Reload
C/T Mode
Value
62.5 K 12 MHz 1 0 2 FF
19.2 K 11.059 MHz 1 0 2 FD
9.6 K 11.059 MHz 0 0 2 FD
4.8 K 11.059 MHz 0 0 2 FA
2.4 K 11.059 MHz 0 0 2 F4
1.2 K 11.059 MHz 0 0 2 E8
135.5 11.059 MHz 0 0 2 1D
110 6 MHz 0 0 2 72
110 12 MHz 0 0 1 FEEB

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 Part 1

Intel 8051: Interrupt Control

7 6 5 4 3 2 1 0
IE EA - - ES ET! EX1 ET0 EX0

 EA: Enable/Disable all interrupts

– If EA=0 no interrupts will be acknowledged
– If EA=1 each interrupt source is individually enabled/disbled
 ES: Serial Port interrupt enable bit
 ET: Timer interrupt enabled bit
 EX: External interrupt enable bit

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 Part 2

Intel 8051: Interrupt Control

• 5 interrupt sources
IT 0 = 0
• 2 external IN T 0 IE 0
(INT0, INT1)
IT 0 = 1
• 2 timers
(TF0, TF1) TF0

• Serial Port
(RI or TI) IT 1 = 0
IN T E R R U P T
IN T 1 IE 1 SO URCE

IT 1 = 1

TF1

RI
TI

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 Part 3

Intel 8051: Interrupt Control

 External interrupts IT0=0

INT0 IE0
– Level-activated or transition-activated
IT0=1
depending on bits IT0, IT1 in register TCON
– The flags that generate these interrupts are
IE0, IE1 in TCON
• Cleared by hardware if the interrupt was transition-activated
• if the interrupt was level-activated,
external source controls request bits
– If external interrupt is level-activated,
the external source has to hold request active,
until the requested interrupt is actually generated.
– External source has to deactivate the request
before interrupt service is completed,
or else another interrupt will be generated

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 Part 4

Intel 8051: Interrupt Control

 Timer interrupts
– Interrupts are generated by TF0 and TF1 in register TCON
– When a timer interrupt is generated, the flag that generated it is
cleared by hardware when the service routine is vectored to
 Serial Port interrupt
– generated by the logical OR of bits RI and TI in register SCON

TI
RI

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 Part 5

Intel 8051: Interrupt Control

7 6 5 4 3 2 1 0
IP - - - PS PT1 PX1 PT0 PX0

 Priority bit=1: High Priority; Priority bit=0: Low Priority

 PS: Serial Port priority bit
 PT: Timer priority bit
 PX: External priority bit

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 Part 6

Intel 8051: Interrupt Control

 A low-priority interrupt can be interrupted by a higher priority
interrupt, but not by another low-priority interrupt
 A high priority interrupt
cannot be interrupted by any other interrupt source
 If two requests are received simultaneously,
the request of higher priority level is serviced
 If requests of the same priority level are received simultaneously,
an internal polling sequence determines which request is serviced
– ``priority within level'' structure is only used
to resolve simultaneous requests of the same priority level.

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 Part 7

Intel 8051: Interrupt Control

Interrupt Priority
within Level Polling Sequence
1 (Highest) External Interrupt 0
2 Timer 0
3 External Interrupt 1
4 Timer 1
5 (Lowest) Serial Port

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 Part 8

Intel 8051: Interrupt Control

 The INT0 and INT1 levels are inverted and latched
into the Interrupt Flags IE0 and IE1 at S5P2 of every machine cycle
 Serial Port flags RI and TI are set at S5P2
 The Timer 0 and Timer 1 flags, TF0 and TF1,
are set at S5P2 of the cycle in which the timers overflow
 If a request is active and conditions are right,
a hardware subroutine call to the requested service routine
will be the next instruction to be executed
 In a single-interrupt system, the response time is always
more than 3 cycles and less than 9 cycles

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 Part 1

Intel 8051: Reset

 The reset input is the RST pin, which has a Schmitt Trigger input
 Accomplished by holding the RST pin high
for at least two machine cycles (24 oscillator periods)
while the oscillator is running
 The RST pin is sampled during S5P2 of every machine cycle
 While the RST pin is high,
the port pins, ALE and PSEN are weakly pulled high
 Driving the ALE and PSEN pins to 0 while reset is active
could cause the device to go into an indeterminate state

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 Part 2

Intel 8051: Reset

S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3

RST
IN T E R N A L R E S E T S IG N A L
SAM PLE SAM PLE
RST RST

ALE

PSEN

P0 IN IN IN IN IN IN
S. A 0 -A 7 S. A 0 -A 7 S. A 0 -A 7 S. A 0 -A 7 S. A 0 -A 7 S.
IN IN IN IN IN IN

1 1 O S C . P E R IO D S 1 9 O S C . P E R IO D S
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Intel 8051: Power On Reset
 RST pin must be held high long enough to allow the oscillator to
start up plus two machine cycles
 The oscillator start-up time depend on the oscillator frequency
 Port pins will be in a random state until the oscillator has started
and the internal reset algorithm has written 1s to them
 Powering up the device without a valid reset could cause the CPU
to start executing instructions from an indeterminate location

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Intel 8051: EPROM Versions
 Electrically programmable by user
 Relative slow
 Limited number of erase/write cycles

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Intel 8051: OTP Versions
 One Time Programmable
 It is standard EPROM without erasing window
 It is used for limited production

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Intel 8051: FLASH Versions
 Supports in-system and in-board code changes
 Electrically erasable
 Reduces code inventory and scrap
 Simplifies the task of upgrading code and
reduces upgrade cycle time
 Provides just-in-time system software downloads
 Truly non-volatile

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Intel 8051: The On-Chip Oscillator
 Intel 8051 microcontrollers
have an on-chip oscillator Q UARTZ CRYSTAL O R 8051
 resonators are connected C E R A M IC R E S O N A T O R
between XTAL1 and XTAL2
pins
 external oscillators (HMOS C1
XTAL2
or CMOS)

C2
XTAL1
VSS

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Intel 8051: Power Management
 Low power devices
 Power saving
 Voltage monitoring

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Intel 8051: Power Reduction Modes
 CHMOS versions provides power reduced modes of operations
 There are two power reducing modes Idle and Power Down
 In the Idle mode oscillator continues to ran
Interrupt, Timer and Serial Port blocks continue to be clocked
clock signal is gated off to the CPU
 In the Power Down mode the oscillator is frozen

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 Part 1

Intel 8051: Instruction Set

Arithmetic Operations
ADD Addition
ADDC Addition with Carry Flag
SUBB Subtraction
INC Increment
DEC Decrement
MUL Multiply
DIV Divide
DA Decimal Adjust Accumulator

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 Part 2

Intel 8051: Instruction Set

Logical Operations
AND And
ORL Or
XRL Exclusive-Or
CLR A Clear (Accumulator)
CPL A Complement
RL A Rotate Left
RLC A Rotate Left through Carry Flag
RR A Rotate Right
RLC A Rotate Right through Carry Flag
SWAP A Swap nibbles within Accumulator
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 Part 3

Intel 8051: Instruction Set

Data Transfer
MOV Move
MOVC Move Code byte
MOVX Move External RAM byte/word
PUSH Push direct byte on stack
POP Pop direct byte from stack
XCH Exchange
XCHD Exchange low order Digit

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 Part 4

Intel 8051: Instruction Set

Boolean Variable Manipulation
CLR Clear bit/flag
SET Set bit/flag
CPL Complement bit/flag
ANL AND bit and flag
ORL OR bit and flag
MOV Move bit

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 Part 5

Intel 8051: Instruction Set

Program and Machine Control #1
ACALL Absolute Subroutine Call
LCALL Long Subroutine Call
RET Return from Subroutine
RETI Return from interrupt
AJMP Absolute Jump
LJMP Long Jump
SJMP Short (Relative) Jump
JMP @A+DPTR Jump indirect relative to the DPTR

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 Part 6

Intel 8051: Instruction Set

Program and Machine Control #2
JZ Jump if Accumulator is Zero
JNZ Jump if Accumulator is Not Zero
JC Jump if Carry flag is set
JNC Jump if No Carry flag
JB Jump if Bit set
JNB Jump if Bit Not set
JBC Jump if Bit set & Clear bit
CJNE Compare and Jump if Not Zero
DJNZ Decrement and Jump if Not Zero
NOP No Operation
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 Part 7

Intel 8051: Instruction Set

Instructions that affect Flag Settings #1
C OV AC
ADD X X X
ADDC X X X
SUBB X X X
MUL 0 X
DIV 0 X
DA X
RRC X
RLC X

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 Part 8

Intel 8051: Instruction Set

Instructions that affect Flag Settings #2
C OV AC
SET C 1
CLR C 0
CPL C X
ANL X
ORL X
MOV C, bit X
CJNE X
Operations on PSW X X X

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Intel 8051: Addressing Modes
 Immediate Addressing MOV A,#20h
 Direct Addressing MOV A,30h
 Indirect Addressing MOV A,@R0
– refers to Internal RAM, never to an SFR
 External Direct MOVX A,@DPTR
– only two commands that use External Direct MOVX @DPTR,A
– DPTR holds the correct
external memory address
 External Indirect MOVX @R0,A
 Code Indirect MOVC A,@A+DPTR

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 Part 1

Intel 8051: Keil C Compiler

 Keil Compiler C51 includes extensions (for ANSI C) for:
– Memory Types and areas on the 8051
– Memory Models
– Memory Type Specifiers
– Variable Data Type Specifiers
– Bit variables and bit-addressable data
– Special Function Registers
– Pointers
– Function Attributes

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 Part 2

Intel 8051: Keil C Compiler

 Program Memory
– code specifier refers to to the 64Kbyte code memory
char code text[] = “ENTER PARAMETER”;
– Accessed by opcode MOVC @A+DPTR
 Program Memory is read only; it cannot be written to
 It can reside within 8051 CPU, it may be external, or both
 Program code, including all functions and library routines are
stored in program memory

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 Part 3

Intel 8051: Keil C Compiler

 Data Memory
– Up to 256 bytes of internal data memory are available
depending upon the 8051 derivate
– data refers to the first 128 bytes of internal memory
char data var1;
– idata refers to all 256 bytes of internal data memory
generated by indirect addressing
float idata x,y,z;
– bdata refers to 16 bytes of bit-addressable memory
in the internal data memory (20h to 2Fh)
char bdata flags;

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 Part 4

Intel 8051: Keil C Compiler

 External Data Memory
– xdata specifier refers to any location
in the 64KByte address space of external data memory
unsigned long xdata array[100];
– pdata specifier refers to only 1 page of 256 bytes
of external data memory
unsigned char xdata vector[10][4][4];

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 Part 5

Intel 8051: Keil C Compiler

 Special Function Register Memory
– SFRs are declared in the same fashion as other C variables
– sfr (rather then char or int)
sfr P0 = 0x80; /*Port0, address 80h*/
– sfr16 access 2 SFRs as 16-bit SFR (8051 derivatives)
sfr16 T2 = 0xCC /*Timer 2; T2L 0CCh, T2H 0CDh)
– sbit allows to access individual bits within an SFR
sfr PSW=0xD0;
sfr IE=0xA8;
sbit EA=IE^7;
sbit OV=0xD0^2;
sbit CY=0xD7;

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 Part 6

Intel 8051: Keil C Compiler

 Unique C51 Data Types
– bit
static bit done_flag=0;
– sbit
sbit EA= oxAF; /*defines EA to be the SFR bit at 0xAF*/
– sfr(Special Function Registers, 0x80-0xFF)
sfr P0 = 0x80; /* Port-0, address 80h*/
sfr P2 = 0xA0; /* Port-2, address 0A0h */
– sfr16
sfr16 T2=0xCC; /* Timer 2: T2L 0CCh, T2H 0CDh

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 Part 7

Intel 8051: Keil C Compiler

 Memory Models
– SmallModel -
all variables, by default, reside in the internal data memory
• All objects, as well as stack must fit into internal RAM
– Compact Model -
all variables, by default, reside in one page of external data memory
• Can accommodate a maximum of 256 variables
• Slower then small model
– Large Model -
all variables, by default, reside in external data memory
• The Data Pointer (DPTR) is used for addressing
• Memory access is inefficient
• Generates more code then small and compact model

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 Part 8

Intel 8051: Keil C Compiler

 Memory-specific Pointers
– Include a memory type specification in the pointer declaration
– May be used to access variables in the declared memory area only
char data *str;
int xdata *numtab;
long code *powtab;

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 Part 9

Intel 8051: Keil C Compiler

 Function Declarations Extensions allow to:
– Specify a function as an interrupt procedure
– Choose register bank used
– Select the memory model
– Specify reentrancy
[return_type] funcname ([args]) [{small|compact|
large}]
[reentrant][interrupt n][using n]
• small, compact, large - memory model
• reentrant - recursive function
• interrupt - interrupt function
• using - specify register bank

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 Part 10

Intel 8051: Keil C Compiler

 Function Parameters and the Stack
– The stack pointer on the 8051 access internal data memory only
– C51 locates the stack area immediately following
all variables in the internal data memory
– The stack pointer access internal data memory inirectly
– C51 assigns a fixed memory location for each function parameter
– Only return address is stored on the stack
– Interrupts fuctions switch register banks and
save the values of few registers on the stack
– By default, the C51 compiler passes up to three arguments in registers

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 Part 11

Intel 8051: Keil C Compiler

 Passing Parameters in Registers

Argument char int long

generic ptr
Number 1 byte ptr 2 bytes ptr float

1 R7 R6&R7 R4-R7 R1-R3

2 R5 R4&R5 R4-R7 R1-R3

3 R3 R2&R3

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 Part 12

Intel 8051: Keil C Compiler

 Function Return Values

Return Type Register Description

bit Carry Flag

char R7
int R6&R7 MSB in R6, LSB in R7
long R4-R7 MSB in R4, LSB in R7
float R4-R7 32-bit IEEE format
Memory type in R3,
generic ptr R1-R3
MSB R2, LSB R1

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 Part 13

Intel 8051: Keil C Compiler

 Specifying the Memory Model for a Function
#pragma small /*default small model */

extern int calc (char i, int b) large reentrant;

extern int func (char i, float f) large;
extern void *tcp (char xdata *xp, int ndx) small;

int mtest (int i, int y){ /*small model*/

return (i*y + y*i + func(-1, 4.75);}

int large_func (int i, int k) large { /*large model*/

return (mtest(i,k) * 2)}

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 Part 14

Intel 8051: Keil C Compiler

 Specifying the RegisterBank for a Function
void rb_function (void ) using 3 { ... }
– The using attribute affects object code as follows:
• The currently selected register bank is saved on stack
• The specified register bank is set
• The former register bank is restored before the function is exited
– Register banks are useful when processing interrupts or
when using a real-time operating system
– The using attribute may not be used in
functions that returns a value in registers

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 Part 15

Intel 8051: Keil C Compiler

 Register Bank Access
 The REGISTERBANK control directive allows you to specify which
default register bank to use
 Upon reset, 8051 loads the PSW with 00h, which selects register
bank 0. To change this, you sholud:
– Modify the startup code to select a different bank
– Specify the REGISTERBANK control directive along with the new
register bank number
 By default, C51 generates code that accesses the registers R0-R7
using absolute addresses
 To make a function insensitive to the current bank, it must be
compiled using the NOAREGS control directive

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 Part 16

Intel 8051: Keil C Compiler

 Interrupt Functions
void timer0 (void) interrupt 1 using 2 {
if (++interruptcnt == 4000){
second++;
Interruptcnt=0; }
}
– The interrupt attribute takes an argument
an integer constant in the 0 to 31 value range
– The interrupt attribute affects object code as follows:
• The contains of SFR ACC, B, DPH, DPL and PSW,
when required, are saved on stack
• All working registers are stored on stack
if a register bank is not specified
• SFRs and working registers are restored before exiting function
• The function is terminated by 8051 RETI instruction

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 Part 17

Intel 8051: Keil C Compiler

 Reentrant Function can be shared by several processes at the same
time.
 When a reentrant function is executing, another process can interrupt it
and then begin to execute that same function. The reentrant functions
may be called recursively:
int calc (char i, int b) reentrant {
int x;
x=table[i];
return (x*b);
}
 Reentrant functions can be called simultaneously by two or more
processes.
 Reentrant functions are often required in real-time applications or when
interrupt and non-interrupt code must share a function.

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 Part 18

Intel 8051: Keil C Compiler

 Functions may be selectively defined as reentrant, using the
reentrant attribute.
 For each reentrant function, a reentrant stack area is simulated in
internal or external memory.
 The following rules apply to reentrant functions:
– bit type arguments or local variables may not be used
– must not be called from alien functions or using alien attribute
– may have other attributes like using or interrupt
– return addresses are stored in the 8051 hardware stack
– functions using different memory models may be intermixed
– each of three reentrant models (small, compact and large) contains its
own reentrant stack and SP

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 Part 19

Intel 8051: Keil C Compiler

 Control directives are used to control the operation of the compiler and
can be specified after the filename on the command line or within a
source file using the #pragma directive:
C51 testfile.c SYMBOLS CODE DEBUG
or
#pragma SYMBOLS CODE DEBUG

 Directive categories:
– source controls define macros on the command line and determine the name
of the file to be compiled)
– object controls affect the form and content of the generated object module;
allow you to specify the optimizing level or include debugging information in
the object file
– listing controls govern various aspects of the listing file (format and specific
content)

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 Part 20

Intel 8051: Keil C Compiler

 The C51 is an optimizing compiler.
 The C51 provides six different levels of optimizing:
– constant folding, simple access optimizing, jump optimizing
– dead code elimination, jump negation
– data overlaying
– peephole optimizing
– register variables, extended access optimizing, local common
subexpression elimination, case/switch optimizing
– global common subexpression elimination, simple loop optimizing
– loop rotation

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 Part 21

Intel 8051: Keil C Compiler

 General optimizations:
– constant folding: several constant values occurring in an expression
or address calculation are combined as a constant
– jump optimizing: jumps are inverted or extended to the final target
addresses when the program efficiency is thereby increased
– dead code elimination: code which cannot be reached is removed
– register variables: automatic variables and function arguments are
located in registers when possible
– parameter passing via registers: a maximum of three function
arguments can be passed in registers
– global common subexpression elimination: identical subexpressions
or address calculations that occur multiple times in a function are
calculated only once

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 Part 22

Intel 8051: Keil C Compiler

 8051 - specific optimizations
– peephole optimization: complex operations are replaced by simplified
operations when memory space or execution time can be saved as a
result
– extended access optimizing: constants and variables are included
directly in operations
– data overlaying: data and bit segments of functions are overlaid with
other data and bit segments by the linker/locator
– case/switch optimization: any switch and case statements are
optimized by using a jump table or string of jumps

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 Part 23

Intel 8051: Keil C Compiler

 Options for code generation:
– OPTIMIZE(SIZE): common C operations are replaced by subprograms,
thereby reducing the program code
– NOAREGS: C51 no longer uses absolute register access; program
code is independent of the register bank
– NOREGPARAMS: parameter passing is always performed in local data
segments

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 Part 24

Intel 8051: Keil C Compiler

 You can easily interface C51 to routines written in 8051 assembler
 For an assembly routine to be called form C, it must be aware of
the parameter passing and return value conventions used in C

Function parameters
 By default C functions pass up to three parameters in registers.
The remaining parameters are passed in fixed memory locations.
 Functions that pass parameters in registers are prefixed with the
underscore character (_functionName)

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 Part 25

Intel 8051: Keil C Compiler

Parameter passing in registers
arg.no. char, 1byte ptr. Int, 2byte ptr long,float gen.ptr
1 R7 R6&R7 R4-R7 R1-R3
2 R5 R4&R5 R4-R7 R1-R3
3 R3 R2&R3 R1-R3

func1 (int a) - a is passed in R6 and R7

func2 (int b, int c, int *d) - b is passed in R6&R7, c in R4 & R3, d in R1, R2 & R3
func3 (long e, long f) - e is passed in R4, R5, R6 & R7, f cannot be located in
registers
func4(float g, char h) - g is passed in R4, R5, R6 & R7, h cannot be passed in
registers

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 Part 26

Intel 8051: Keil C Compiler

Parameter passing in fixed memory locations
 Parameters passed to assembly routines in fixed memory locations use
segments named ?function_name?BYTE and ?function_name?BIT to
hold the parameter values passed to the function function_name.

Function return values

 Function return values are always passed using CPU registers:
return type register
bit carry flag
char/unsigned char/1-byte pointer R7
int/unsigned int/2-byte pointer R6 & R7
long/unsigned long/float R4 - R7
generic pointer R1-R3

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 Part 27

Intel 8051: Keil C Compiler

Example:

#pragma SRC
#pragma SMALL
unsigned int asmfunc1(unsigned int arg) { return (1+arg); }

NAME ASM1
?PR?_asmfunc1?ASM1 SEGMENT CODE
PUBLIC _asmfunc1
RSEG ?PR?_asmfunc1?ASM1 USING 0
_asmfunc1: mov A,R7
add A,#10h
MOV R7,A
CLR A
ADDC A,R6
MOV R6,A
?C0001: RET END

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Intel 8051: Manufacturers
 AMD  OKI
 ARM Microcontrollers  Philips

 ARC Cores  Siemens

 Atmel  SMC
 Dallas
 SSI
 Hitachi semiconductors  Texas Instruments
 Intel  ZiLog
 ISSI  etc.

 Matra
 Microchip

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Intel 8051: Additional Features
 Watch Dog Timers
 Clock Monitor
 Resident Program Loader
 Software protection
 P Supervisory Circuit

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Watch Dog Timers
 Provides a means of graceful recovery from a system problem
 If the program fails to reset the watchdog at some predetermined
interval, a hardware reset will be initiated
 Especially useful for unattended systems

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Clock Monitor
 If the input clock is too slow, a clock monitor can shut the
microcontroller down
 Usually software controlled status (on/off)

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Resident Program Loader
 Loads a program by initializing program/data memory from either a
serial or parallel port
 Eliminates the erase/burn/program cycle (typical with EPROM’s)
 Allows system updating from an offsite location

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Software protection
 Protect unauthorized snooping (reverse engineering,
modifications, piracy, etc.
 Only OTPs and Windowed devices option

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 Part 1

P Supervisory Circuit
 Functions:
 P reset (active low or high) PF1 1 16 O UT
– Manual reset input PF0 2 15 B A TT O K
– Two stage power fall warning Vcc 3 14 B A TT
– Backup-battery switchover W DI 4 M A X IM 13 B A TT O N
– Write protection of RAM G ND 5 M AX807 12 C E IN
– 2.275 threshold detector M R 6 11 C E O UT
L O W L IN E 7 10 W DO
– Battery OK flag indicator
RESET 8 9 RESET
– Watch Dog timer

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 Part 2

P Supervisory Circuit
PIN NAME FUNCTION

1 PFI Power-Fall Input

2 PFO Power-Fall Output
3 VCC Input Supply Voltage
4 WDI Watchdog Input
5 GND Ground
6 MR Manual-Reset Input
7 LOW LINE Low-Line Comparator Input
8 RESET (H) Active-High Reset Output

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 Part 3

P Supervisory Circuit
PIN NAME FUNCTION

9 RESET (L) Active-Low Reset Output

10 WDO Watchdog Output
11 CE OUT Chip-Enable Output
12 CE IN Chip-Enable Input
13 BATT ON Battery On Output
14 BATT Backup-Battery Input
15 BATT OK Battery OK Signal Output (Vbatt>2.265)
16 OUT Output Supply Voltage to CMOS RAM

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 Part 4

P Supervisory Circuit
+5V

0 .1 u F 0 .1 u F

Vcc BATT OUT

ON
BATT

REAL
CM OS
T IM E
RAM
CLOCK
CE OUT
OT HER M R
SY STEM
RE SET
ADDRESS
SO URCES C E IN
DECODE
PUSH M A X IM
BUTTON M A X807 ADDRESS
S W IT C H W DI I/O
L O W L IN E N M I( IN T )
RESET
+12V
RESET RESET
BATT OK IN T

uP
PFI
PFO + 1 2 V F A IL U R E
W DO W A T C H D O G F A IL U R E
G ND

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Comparative Characteristics
Clock V ROM RAM Timers/ communi- Additional
Manufacturer I/O
[MHz] [V] [KB] [bytes] Counters cation Features
2.7 to 128 to full duplex
Atmel 24
6
2 to 8
256
32 Up to 3
serial port
watchdog,
256-byte
two serial power monitor,
Dallas 25 to 33 0 to 16 to 1.2 3
USARTs address and
kbyte
data encryption
4 to 8 channel 8-
0.5 to 2.7 to 128 to 24 to bit ADC,
Intel 24 6
0 to 32
256 56
2 to 3 serial port
watchdog,
PWM
ROM
2.7 to 128 to serial port, protection and
Matra 42
6
4 to 32
256
32 2 to 3
I2C secret tag,
watchdog
2.7 to 128 to
Oki 24
5.5
0 to 16
256
32 2 to 3 serial port
256-byte two watchdog
two serial
Siemens 18 to 40 8 to 32 to 2.2- 56 3 to 4
ports
timers, 16-bit
kbyte MPY/DIV unit

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Intel 8051-Design Example
The complete design project using the 8051 microcontroller will be
presented here. All design phases mentioned earlier will be shown:

– specification

– circuit diagram

– pcb layout

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Specification
The idea is to design a small, simple PCB for test purposes. The
device will have:

– 8 driver outputs (ie. LEDs, relays)

– a speaker output

– a light sensor input

– 3 extra inputs

– optional serial port

The device will be based on Atmel AT89C2051microprocessor, a 20

pin 8051 variant with FLASH program memory.
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Circuit Diagram

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 Circuit Description
 The battery power supply is connected on terminals T1 &T2. While the circuit diagram specifies 3v/4.5v battery, the part ULN2803 needs 4.5v-5v battery

to get proper operation.


Switch SW2 allows the PCB to be turned on and off.


Capacitor C1 provides a reset signal to the microprocessor.

 XTAL1 provides the oscillator timing component for the microprocessor. It is important to use a crystal for XTAL1, not a ceramic resonator - prototype

testing shows that a ceramic resonator gives problems unless capacitors to ground are placed on X1 & X2.


Diode D1 provides some protection for the microprocessor in case of transients or misconnection of the battery


Optodarlington TR1 is the light sensor


Pot VR1, as labelled, adjusts the sensitivity of the light sensor

 Resistor R9 provides current limiting when full illumination is on TR1 at max sensitivity


The symbol PCB LAM#1 is a record of the PCB laminate ID number, and ensures the PCB laminate appears in the parts list


The symbol SKT1 is a record of the need for a socket for IC1, and ensures that the socket appears in the parts list

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 Circuit Description

TR2 is a switch used to sense illumination (On=TR1 illuminated)


Pin 6 of the micro is the LiteOn input (Low=TR1 illuminated)


SW1 is in parallel with the LiteOn input - pushing SW1 is like illuminating TR1


Resistors R12 & R13 pull up the open collector outputs P1.0 and P1.1 of IC1


IC2 is the driver IC, with several hundred milliamps drive capability on each output

 R1-R8 limit the current that can be taken from each output of IC2, and are most useful when LEDs are connected directly to pins L1-L8. If other devices

are used, such as relays, the values may of R1-R8 may have to be changed, or replaced with links.


R10 limits the current from IC1 into the base of TR3

 TR3 is a switch transistor that drives the sounder output (P3.7 Low=Sounder driven high)


R11 provides the class A load resistor for the sounder output


C2 Capacitively couples the speaker to TR3 and R11.


C3 provides some supply decoupling.

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PCB Diagram
Central to the board are the
two IC's: The AT89C2051 (in
an IC socket) and ULN2803
driver. The bank of resistors
to the right of the ULN2803
are primarily for limiting the
current through LEDs, when
they are being driven direct
from the outputs. You may
wish to use another value
instead of the 27 ohm shown
on the circuit. The circuitry
to the left of the CPU is
primarily for the light sensor
- this is just a simple
darlington phototransistor,
sensitivity pot and switch
transistor.
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PCB Artwork, overlay
The overlay
diagram is used
for the silkscreen
(legend) of the
circuit board.

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PCB Artwork, top layer
The top layer
diagram is used
for the tracks
that go on the
component side
of the circuit
board.

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PCB Artwork, bottom layer
The bottom layer
diagram is used for
the tracks that go on
the solder side of the
circuit board. The
layer is printed as if
you are viewing
through the circuit
board (this is a
convention used so
that the layers line
up) and will have to
be reversed left-for-
right before the
copper tracks are
printed.

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PCB Art, Hole drilling diagram

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 Parts description


RB.06/.15 - Radial polarised capacitor, 0.060 inch pitch lead space, 0.15 inch diameter


RB.1/.2 - Radial polarised capacitor, 0.1 inch (2.5mm) pitch lead spacing, 0.2 inch (5mm) diameter


DIODE0.3 - Axial diode, 0.3 inch (7.5mm) pitch lead spacing


DIP20 - IC, standard 0.3 inch pitch 20 pin DIP package


DIP18 - IC, standard 0.3 inch pitch 18 pin DIP package


TP - Test point or terminal


PCLAMINATE - The part being specified here is the etched PCB laminate


AXIAL0.4 - 0.4 inch pitch unpolarised component (eg resistor)


TV-06A - Push button switch, zippy brand


S2020SMT - Slide switch


TO-92A - Standard TO-92 package, with staggered leads, 0.1 inch pitch spacing


VR4 - Adjustable pot, staggered leads, 0.1 inch pitch spacing


XTAL2 - Crystal, HC49/4H (also called HC49Small) package

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 Parts notes


2.2UF50VMM - Radial polarised capacitor, Microminiature style, eg Rubycon, elna
 AT89C2051 - Atmel microprocessor, see Atmel site for data and a programmer


ULN2803A - Manufacturer: Allegro (formerly known as Sprague)


27E - Resistor, value 27 ohm - substitute if required for different outputs
 MEL12 - Phototransistor - many substitutes will work, but darlington types offer the best sensitivity. We have used BP103B

(Farnell 212-763 in Australia). Flat goes toward TR2 for two leaded devices.
 3.57945Mhz - Frequency depends on application program. Use a crystal, rather than a ceramic resonator (otherwise fit extra
capacitors to gnd on X1 and X2).

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Using the Device
The diagram on the
left shows a typical
circuit using the
HSETI PCB, with
the optional serial
port in place also.
The serial port
does not have
strict RS232 level
signals, but will
work with just
about all PC clones
with reasonable
cable lengths.

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