X86

Session_10

80386 contd.

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386 nonpipelined read cycles

CLK2
(INPUT)
BE0# - BE3# , A2-A31,
M/IO# , D/C# , W/R#

CYCLE 1
T1
T2

CYCLE 2
T1
T2

VALID 1

VALID 2

ADS#
NA# I/P
READY#
I/P
LOCK#
Out put
D0-D31
IN
(Input during read)

VALID 1

VALID 2
IN1

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IN

386 nonpipelined read cycles

Each read operation requires
two states , T1 & T2
READY# is made low during T2
so that no wait states are
inserted

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386 nonpipelined read cycles

ADS# is used for address pipelining
Address is held by the latches
386 address pins point to the next
address
External circuitry asserts NA# signal to
tell the 386 when to output the address
for the next operation
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80386 Functional Units

EXECUTION UNIT

SEGMENT UNIT

CONTROL UNIT

SEGMENT
REGISTERS

TRANSLATION
LOOKASIDE
BUFFER

SEGMENT

PAGE
TRANSLATOR

DATA UNIT
PROTECTION
TEST UNIT

TRANSLATOR

DECODER
INSTRUCTION

QUEUE

DECODE UNIT

PREFETCH
QUEUE
PREFETCHER

PAGE UNIT

BUS
INTERFACE

BUS UNIT

PREFETCH UNIT

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80386 Functional Unit

(Contd.)

The BIU interfaces between the

80386 with memory and I / O
The code PREFETCH UNIT prefetches
instructions ,stores them in a 16 byte
queue
The INSTRUCTION DECODE UNIT
translates instructions into
microcodes
The EXECUTION UNIT acts on the
microcodes from the instruction
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queue

80386 Functional Unit

(Contd.)

The SEGMENTATION UNIT translates

logical addresses into linear
addresses
The PAGING UNIT , if enabled ,
translates these linear addresses
into physical addresses. If not
enabled , then linear addresses and
physical addresses are identical
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80386 Functional Unit

(Contd.)

The Execution Unit comprises

Control unit -having microcode and
parallel hardware
Data unit - having ALU and 8 GPRs
and a 64 bit barrel shifter
The protection unit checks for
segmentation violations under the
control of microcode
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Processing Modes of 80386

1. Protected mode [ normal 32 bit
application of 80386 ]
2. Real address mode or Real mode
[ A fast 8086 mode with a few
new
instructions]
3. Virtual 8086 mode or V86 mode
[ goes
back and forth between V86
mode
and
the protected mode
]
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80386 Real Mode

Upon reset or power - up , the 80386
operates in real mode
In this mode,it can access all the 8086
registers along with the 80386 32 -bit
registers
Instructions can refer to AL,AH,AX or EAX
Physical address is calculated with the
segment

base , offset mechanism

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80386 Real Mode

Uses address space 00000 - 003FF for the
IVT
It has a set of debug registers
A software debugger can load breakpoint
addresses in these registers

Control registers CR0 - CR3 are used and

the lower 16 bits of CR0 correspond to
machine Status word of 80286
CR1 is reserved ; CR2 and CR3 are used for
paging mode

Linear addresses are the physical

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addresses

11

Real Mode

(Contd.)

Uses a combination of:

16-bit segment registers (CS, DS, ES, FS,
GS, SS)
16-bit offsets (depends on addressing
modes)
Effective addresses are 20 bit
0
That's 1MB 15
address space (with
a 16-bit
xxxx xxxx xxxx xxxx 0000
Segment
processor!)
+
15
0
Offset
0000 xxxx xxxx xxxx xxxx
=
19
0
Physical
xxxx xxxx xxxx xxxx xxxx
Address
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386 -Protected Mode

386 is switched from real mode to
protected mode by setting the LSB of the
CR0 register
Increases the linear space to 4GB and
permits the execution of virtual memory
programs of 64 tera bytes (2^46 bytes)

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386 -Protected Mode

Can run all existing 8086 and 80286
programs with on-chip memory
management and protection features
Includes new instructions to support
multitasking, multiuser operating systems

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80386 Protected Mode

32-bit Offset

L o gi c al
Selector

A dd r e s

Physical
Memory

Offset
Limit

Descriptor

Linear
Address

Base
Address

Offset

GDT or LDT
32-bit Address

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Descriptor Table
Two types of descriptor tables
global consisting of
segment descriptors for the OS
segment
segment descriptors for the user tasks

and others

local descriptor table for each task

Tasks share a GDT and the

memory area defined in it
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How Protection Works

Each time a task loads a segment register,
the CPU performs many checks
if the descriptor table indexed contains a valid
descriptor
if the segment descriptor is of the right type
to be loaded into the specified segment
register cache
For e.g. a descriptor for a read only data segment
cannot be loaded into the SS register

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How Protection Works

User tasks are protected from one
another by providing individual LDTs
System software ,such as the OS
kernel,is protected by
making the code segments only
executable
By having different privilege levels
OS kernel having the highest priority level
0,system services such as BIOS procedures at
1,custom device drivers at 2,application
programs and user tasks at the lowest level

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How Protection Works

The descriptor privilege level is
referred as the DPL
The privilege level of an executing task
is the current privilege level CPL
The privilege level encoded when a
program needs to access a data
segment,is requesting privilege level
RPL
A task cannot directly access a segment
that has a higher DPL
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Call Gates
A gate is a special type of descriptor
put in the GDT or in an LDT
When a program calls a procedure in
another segment,the selector for the
segments call gate is put in the CS
register and the call gate descriptor in
the hidden part of the CS
This indirect access through the call
gate does another privilege check
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