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Slides for Chapter 5 prepared by Dr. Saeid Belkasim, Dept. of Computer Science, GSU
Addressing Mode
I=0 : Direct,
I=1 : Indirect
Direct Addressing
Occurs When the Operand Part
Contains the Address of Needed Data.
IR
110101011001
01011001
AR
Memory
DR
000000001111
Indirect Addressing
Occurs When the Operand Contains the
Address of the Address of Needed Data.
IR 1 1 0 1 0 1 0 1 1 0 0 1
AR
10 01 10 1 1 0 10 1
Memory
DR
000000000101
Accumulator
Instruction
Temporary
Address
Program
Counter(PC) :
Input
Number
Register
of bits
name
16
Data register
12
Address register
16
Accumulator
16
Instruction register
12
Program counter
16
Temporary register
8
Input register
8
Output register
Register
Function----------------------Holds memory operands
Holds address for memory
Processor register
Holds instruction code
Holds address of instruction
Holds temporary data
Holds input character
Holds output character
s0 s1 s2
7
Address
READ
AR
LD
CLR
INR
PC
LD
INR
CLR
DR
LD
Adder
& Logic
CLR
INR
AC
LD
Bus
CLR
INR
INPR
IR
TR
LD
LD
INR
CLR
OUTR
LD
Clock
When
12 11
12 11
24 = 16 possible instructions
Op-code 0111 reserved for register-reference
instructions
How many possible register-reference
instructions?
212 = 22210 = 4K = 4096 possible r-r instructions
(only 12 are used)
12 11
24 = 16 possible instructions
Op-code 1111 reserved for input/output
instructions
I=0 : Direct,
I=1 : Indirect
15 14
12
11
I Opcode
Address
Register-reference instruction
12
11
0 1 1 1
Register Operation
Input-Output instruction
Fxxx(F800 ~ F040) : INP, OUT, ION, SKI,
15 14
12
1 1 1 1
11
I/O Operation
In s t r u c t io n r e g is t e r ( IR )
14
13
12
11 - 0
3 8
decoder
7 6 5 4 3 2 1 0
O t h e r in p u t s
D0
T
15 14
.
.
.
.
.
.
.
.
.
T 15
4 16
decoder
4 - b it
seq uence
c o u n te r
(S C )
1 0
In c re m e n t ( IN R )
C le a r ( C L R )
C lo c k
.
.
.
15
C o n tro l
lo g ic
g a te s
C o n tro l
o u tp u ts
microoperations
T0:
T1:
T2:
11),IIR(15)
ARPC
IRM[AR],PCPC+1
D0,...,D7DecodeIR(1214),ARIR(0
T0: Since only AR is connected to the address inputs of memory, the address of
instruction is transferred from PC to AR.
1. Place the content of PC onto the bus by making the bus selection inputs S2S1S0
= 010.
2. Transfer the content of the bus to AR by enabling the LD input to AR
( ARPC).
T1: The instruction read from memory is then placed in the instruction register IR.
At the same time, PC is incremented to prepare for the address of the next
instruction.
1. Enable the read input of the memory.
2. Place the content of memory onto the bus by making the bus selection inputs
S2S1S0 = 111. (Note that the address lines are always connected to AR, and we
have already placed the next instruction address in AR.)
3. Transfer the content of the bus to IR by enabling the LD input to IR
(IRM[AR]).
4. Increment PC by enabling the INR input of PC ( PCPC+1).
T2: The operation code in IR is decoded; the indirect bit is transferred to I; the
address part of the instruction is transferred to AR. (See the common bus skeleton
diagram.)
D7IT3:
ARM[AR],indirectmemory
transfer
D7IT3:
Nothing,directmemory
transfer
D7IT3:
Executearegisterreference
instruction
D7IT3:
Executean
I/Oinstruction
Figure: Control
circuit for
instruction fetch.
This is a part of the
control circuit and
demonstrates the
kind of wiring
needed.
REGISTER-REFERENCE INSTRUCTIONS
The 12 register-reference instructions are recognized by I = 0 and
D7 = 1 (IR(12-14) = 111). Each operation is designated by the
presence of 1 in one of the bits in IR(0-11). Therefore D7IT3 r =
1 is common to all register-transfer instructions.
D3T4 : M [ AR] AC , SC 0
PC = 10
PC = 21
0
BSA 135
next instruction
D4T4 : PC AR, SC 0
D5T5 : PC AR, SC 0
BUN 135
Save Return
Address(PC) at 0
Jump to 1(PC=1)
RT0 : AR 0, TR PC
Interrupt
Here
Main Program
255
256
Interrupt
1120
Service Routine
1
BUN
In s tr u c tio n c y c le
=0
F e tc h a n d d e c o d e
in s tr u c t io n
E x e c u te
in s t r u c t io n
=1
In te r r u p t c y c le
S to re re tu rn a d d re s s
in lo c a t io n 0
M [ 0]
P C
=0
IE N
= 1
= 1
B r a n c h to lo c a tio n 1
P C
1
F G I
=0
= 1
IE N
R
F G O
=0
0
0
5-8
5-9
The control unit must make sure that at most one register (or
memory unit) places data onto the bus at one time.
The memory unit is external to the CPU. It always receives its
address from the address register (AR) and makes its data available
to the CPU bus. It receives data from the CPU bus as well.
Read and write signals are supplied by the control unit.
The address registers, program counter (PC) and data register (DR)
each load data onto and receive data from the system bus. Each has a
load, increment and clear signal derived from the control unit. These
signals are synchronous; each register combines these signals with
the system clock to activate the proper function.
Since AR and PC are only 12-bits each, they use the low order 12
bits of the bus.
The accumulator makes its data available on the bus but does not receive data from
the bus.
it receives data from ALU (Adder and Logic) only.
To load data into AC, place it onto the bus via DR and pass it directly through the
ALU.
Note that E, the 1-bit carry flag, also receives its data from the ALU.
The input register, INPR, receives data from an external input port and makes it
available only to AC.
The output register makes its data available to the output port using specific
hardware.
The instruction register, IR, can only be loaded; it cannot be incremented nor
cleared. Its output is used to generate Dis and Tis control signals.
TR is a temporary register. The CPU uses this register to store intermediate results
of operations. It is not accessible by the external programs. It is loaded,
incremented and cleared like the other registers.
Control signals
u T0, T1, ... T6 : Timing signals
u D0, D1, ... D7 : Decoded instruction
u I: Indirect bit
u R: Interrupt cycle bit
The T signals occur in sequence and are never skipped over. The only
two options during a T-state are to proceed to the next T-state or to
return to T state 0.
The D signals decode the instruction and are used to select the correct
execute routine.
I is used to select the indirect routine and also to select the correct
execute routine for non-memory reference instructions.
R is used for interrupt processing and will be explained later.
Control signals
Control signals
I/O configuration
u 8-bit input register INPR
u 8-bit output register OUTR
u 1-bit input flag FGI
u 1-bit input flag FGO
u 1-bit interrupt enable IEN
The Basic Computer has one 8-bit input port and one 8-bit output
port. Each port interface is modeled as an 8-bit register which can
send data to or receive data from AC(7-0). Whenever input data is to
be made available, the external input port writes the data to INPR and
sets FGI to 1. When the output port requests data, it sets FGO to 1. As
will be shown shortly, the FGI and FGO flags are used to trigger
interrupts (if interrupts are enabled by the IEN flag).
Input operation
u Input device makes data available and sets FGI=1.
u If interrupt is enabled, Basic Computer calls interrupt
routine at location 0, which disables further interrupts.
u Interrupt routine reads in and processes data, reenables interrupts and returns. Reading in data resets FGI
to zero.
In the Basic Computer, I/O requests are processed as interrupts. This
process is followed for input requests. The input will only be
processed if interrupts are enabled. It will be ignored, but will remain
pending, if interrupts are disabled.
Output operation
u Output device requests data and sets FGO=1.
u If interrupt is enabled, Basic Computer calls interrupt
routine at location 0, which disables further interrupts.
u Interrupt routine processes and outputs data, re-enables
interrupts and returns. Writing out data resets FGO to zero.
Outputs are handled similarly to inputs. Note that both input and
output interrupts call an interrupt service routine at location 0. There
is only one routine for both input and output, so it must distinguish
between the two. This is where the SKI and SKO instructions become
useful.
Interrupt processing
u An interrupt occurs if the interrupt is enabled (IEN = 1)
AND an interrupt is pending (FGI or FGO = 1).
u Before processing the interrupt, complete the current
instruction!!!
u Call the interrupt service routine at address 0 and
disable interrupts.
It is of the utmost importance to complete the current instruction,
otherwise the CPU will not perform properly.
The interrupt service routine is called by the CPU in a manner
similar to the execution of the BSA instruction.
Interrupt cycle
Activating an interrupt request:
T0 T1 T2(IEN)(FGI + FGO): R
Interrupt cycle:
RT0: AR 0, TR PC
RT1: M[AR] TR, PC 0
RT2: PC PC + 1, IEN 0, R 0, SC 0
An interrupt is asserted by setting R to 1. This occurs when interrupts are enabled
(IEN) and there is either an input or output request (FGI+FGO). We must also have
completed the current fetch cycle (T0T1T2).
When we look at the code to implement the interrupt cycle, we see why we must
wait until after T2 to set R to 1. If we set R to 1 during T0, for example, the next
micro-instruction would be RT1, right in the middle of the interrupt cycle. Since we
want to either perform an entire opcode fetch or an entire interrupt cycle, we dont
set R until after T2.
Input:
1. D0 - D7: Decoded IR(14-12)
2. T0 - T15 : Timing signals
3. I: Indirect signal
4. IR(0-11)
Output:
1. Control inputs of the nine registers, AR, PC, DR, AC, IR, TR, OUTR, INPR, SC
2. Read and write inputs of memory
3. Signals to set, clear, or complement the flip-flops, IEN, R, etc.
4. Select signals, S2, S1, S0, for common bus
5. Control signals to the AC adder and logic circuit
CONTROL OF REGISTERS AND MEMORY
Systematic Design Procedure
1. For a given register, scan the table of microoperations in the previous slides to
find all the statements involving that gate.
2. Translate the associated control functions to Boolean functions.
3. Convert the Boolean expressions into logic gates.
Example: Control of AR
1. The following is the summary of the register transfers associated
with the address register.
RT0:ARPCload
RT2:ARIR(011)load
D7IT3:ARM[AR]load
RT0:AR0clear
D5T4:ARAR+1increment
2. The control functions can be combined into the following Boolean
expressions.
LD(AR)=RT0+RT2+D7IT3
CLR(AR)=RT0
INR(AR)=D5T4
In a similar fashion, the control gates for the other registers and memory can be
derived. For example, the logic gates associated with the read input of memory is
derived by scanning the microoperation table to find the statements that specify a
read operation. The read operation is recognized from the symbol M[AR].
Read= RT1+D7IT3+(D0+D1+D2+D3)T4
12
F ro m B u s
LD
D '7
I
T3
pB6 : IEN 0
RT2 : IEN 0
C LR
R
T0
D
T4
D5T4 : AR AR 1
? M [ AR]
pB7 : IEN 1
IN R
T2
12
AR
D '7
I
T3
J
0
1
p
B7
SET
C lo c k
B6
R
T2
IE N
C LR
KQ(t+1)
1
0
0
1
To Bus
C lo c k
4 4
D5T5 : PC AR
S0
x3
x4
x5
x6
x7
Encoder
S1
S2
Multiplexer
Bus Select
Input
Fig. 5-21
Fig. 2-11
16
16
F ro m D R
8
F r o m IN P R
Adder and
lo g ic
c ir c u it
A c c u m u la t o r
r e g is te r
(A C )
16
LD
Fig. 5-20
C o n tro l
g a te s
IN R
C L R C lo c k
16
To Bus
AC ?
F ro m a d d e r
a n d lo g ic
D
AND
T5
D0T5 : AC AC DR
D1T5 : AC AC DR
D2T5 : AC DR
pB11 : AC (0 7) INPR
ADD
DR
T5
LD
rB9 : AC AC
IN P R
B 11
r
CLR
rB5 : AC AC 1
INR
C O M
SHR
SHL
IN C
C LR
B 11
16
16
AC
LD
IN R
C LR
To Bus
C lo c k
A C ( i)
( O u tp u t o f O R g a te in F ig . 5 - 2 0 )
AND
C
ADD
FA
C
i+ 1
F ro m
IN P R
b it ( i)
Ii ( F ig . 2 - 1 1 )
DR
KQ(t+1)
1
0
0
1
A C ( i)
IN P R
C lo c k
C O M
SHR
A C ( i+ 1 )
SHL
A C ( i- 1 )
J
0
1
LD
* Fig. 2-11
Increment, Clear,
Count
Integration !