Flip- Flops

A basic digital memory circuit

It has 2 stable states

NOR gates ( R-S latch )

( R-S latch )

R (Reset)
Q

0
Q
R=0

1
S=1

Q
0
B

S (Set)
A B B

Property of a NOR gate

B
A=0

Whents like an inverter.

When one I/P is 1, then O/P=0.
Different I/P conditions for R-S latch:
i) R=S=0, current I/P is stored indefinitely
Hold ( becomes cascade of inverters)

ii) R=1, S=0, when we want to store a 0 in the R-S latch.

Q=0, Q 1
iii) R=0, S=1, when we want to store a 1 in the latch.
Q=1, Q 0
iv) R=1, S=1; Forbidden inputs!

Keep state

Unstable
condition

NOR gates ( R-S latch )

( R-S latch )

R (Reset)
Q

0
Q
R=0

1
S=1

Q
0
B

S (Set)
A B B

Property of a NOR gate

B
A=0

Whents like an inverter.

When one I/P is 1, then O/P=0.
Different I/P conditions for R-S latch:
i) R=S=0, current I/P is stored indefinitely
Hold ( becomes cascade of inverters)

Two implementations for R-S latch:

Cross-coupled NOR
R

Cross-coupled NAND
R

Q
Q

Q
S

Hold State

Hold State R=S=1

R=0, S=0

R=S=0

R=1, S=1
5

Forbidden I/Ps

4) The D-Latch
R

R1

R-S

Clk
D

Q
Latch Q

S1

D=1, S=1, R=0

Clk=1
Q

0
Q=1,
D=0, S=0, R=1
Clk=1
Q=0, Q 1
Clk=0 R1,S1=0 (hold state)

Clocked Latch
(level-sensitive clock latch)
see terminology defined
later.

clk

positiv
e edge

positiv
e edge

otherwi
0 or 1
se
6

Keep
Keep
previou previou
s state s state

4) The T-Latch

clk

positiv
e edge

positiv
e edge

otherwi
0 or 1
se

Keep
Keep
previou previou
s state s state

5) The J-K Latch:

Proposed to get rid of the forbidden I/P problem of R-S
i) J=1, K=0: (a) Let Q=1, Q 0 R=0,S=0
Hold state of R-S Q=1, Q 0
(b) Let Q=0, Q 1, R=0, S=1 Q=1, Q 0
ii) J=0, K=1 Q=0, Q 1 using a similar analysis
iii) J=K=0 Hold state
iv) J=K=1, suppose Q=1,Q =0
R=1, S=0 Q=0, Q =1
S=1, R=0 Q=1, Q =0
This type of toggling continues as long as J=K=1, and the latch
is enabled ( CLK=1 below )
K

Q 10

10
R

CLK
J
8

R-S

1
Q

01

01

Keep state

Toggle with clocks rising

edge

Latch classification with respect to response to control signal

Terminology: Note that the terminology below applies to all types of latches:
i)

R-S, D, J-K, T, etc., though the examples are given for the R-S latch.
Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal.
R

Symbol:

R
S

Q
Q

Clock:
Fixed frequency alternating 1 and 0 signal
ii) Clocked or Level-Sensitive Latch:
R
O/P responds to I/Ps only when enb or
Q
clock is at a pre-determined level (high
Clock
or low In this example, it is High)
or
enb

10

Symbol:

R
S

Q
Q

or

CLK

(high enable)

R
S
CLK

Q
Q
(low enable)

iii) Edge-Triggered Flip-Flop (FF) or simply Flip-Flop

O/P will respond to I/Ps only at either:
(a) the positive or rising edge of the enb/clock signal (positive
Symbol:
edge-triggered FF), or
R Q
S Q

CLK

(b) the negative or falling edge of the enb/clock signal (negative

edge-triggered FF).
R Q
Symbol:
S

CLK

Clock:
O/P resp. period for
a low-enable/clock
level sensitive latch

11

O/P response
period for a
positive
edgetriggered
FF.

O/P response
period for a
negative
edge-triggered
FF

O/P response
period for a
HIGH-enable/clock
level-sensitive
latch

Setup Times and Hold Time of FFs and Latches

Assume, positive edge-triggered D-FF

THold relates to propagation delay

of another part of circuit.

D
CLK

TSetup relates to propagation delays of

The high point of
various gates in the FF.
the CLK determines the positive edges arrival.

If negative edge-triggered
TSetup

THold

D
CLK
Negative edge arrival
If D-Latch is high-level sensitive: Tsetup and Thold have to be around the negative edge
of clock (more specifically, when the clock begins to go low), similar to negative edge-triggered.
If D-Latch is low-level sensitive: Tsetup and Thold have to be around the positive
12
edge of clock, similar to positive edge-triggered.

Solutions to Race Condition Problem with Level Sensitive Latches

Solution 1: Master-Slave FF:
Q
R
1

0
S

R-S
Latch

Qm

Qm

1
P
0

1
0

1 Q

Qs

R-S
S

Qs

CLK

Slave R-S is level sensitive.

Master R-S is level sensitive.
Master-Slave J-K is a solution to race-condition problem: Any change in Q, Q
during CLK=0 is not propagated to P, P and hence back to Q, Q during the
same CLK=0. Any change to Q, Q will occur in next CLK=0 period.
J
K

J-K
M-S

(O/P responds when CLK goes

From 1 to 0)

13

Q
Q

Master-Slave J-K works similar

to a J-K latch: E.g. Let
J=1, K=1, CLK=1
Q=1, Q =0 P =1 , P=0
When CLK=0
Q=0, Q =1

Solution 2: Edge-Triggered FF:

HoldsD when
clock goes low

D
R

D
Holds D when
clock goes low

Q responds to
internal S signal;
Q responds to
internal R signal.

CLK

When CLK is 1 D I/P is

internally sampled but
does not appear at the O/P.

D
R

Clk=0

O/P appears (Q=D)

Q
Q

D
14

Q =D

D=1=S
Q=1, Q 0

Q D

D 0R

Clk=0

Clk=1
0

Assume D=1

O/P is held (changing D does not

cause any change in internal
signals in the FF or in its output)

Characteristic Equations of Latches/FFs

The next O/P Q+ defined in terms of the current O/P Q and the I/P.
(FF/Latch is the simplest possible sequential ckt.)
1) R-S Latch Truth Table:
Values at time t
S(t)
R(t)
Q(t)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

15

Q(t)\SR 00
0
0
1
1

01
0
0

11
x
x

Q+ = Q( t+ )
0
Hold
1
0
Reset
0
1
Set
1
x
Forbidden
x

10
1
1

Q+= S+ R Q
(Characteristic equation)

Similarly: Characteristic Equations of

2) J-K,
Q+ = Q K + Q J.
Symbol:
+
3) D-FF, Q = D
T
+
4) Toggle FF/Latch
Q = Q T + QT
or T-FF / Latch
Whenever I/P T is high,
the FF will toggle, i.e., Q+ = Q.
When T=0, Q+=Q.
Of course, these characteristic equations come into play only
when the FF/Latch is enabled.

16

Excitation Table
Reversed Truth Table
What the inputs to FFs should be for given output
transitions (Q Q+)
Q
0
0
1
1

17

Q+
0
1
0
1

R
x
0
1
0

S
0
1
0
x

J
0
1
x
x

K
x
x
1
0

T
0
1
1
0

D
0
1
0
1

 Conversion between FFs

Example: J-K to D
D

Logic

This should
behave like a
D-FF.

Q
Q

CLK

D
Q 0

O/P function = J
0
J=D

Q
D

Function = K
K= D

Map the D,Q input combination to a QQ+ transition

and then map this to J-K excitation required.
Thus, when D=1, Q=0, Q+=1 J,K = 1,x
D=0, Q=0, Q+=0 J,K = 0,x
D=1, Q=1, Q+=1 J,K = x,0
D=0, Q=1, Q+=0 J,K = x,1.
J
D
18

CLK

D-FF
Q
Q

D J-K

Example 2:

should work like a J-K

Excitation Table for D

Q Q+
00
01
10
11
JK
Q
0
1

KQ

D
0
1
0
1

JQ

00

01

11

10

J
0
0
0
0
1
1
1
1

K
0
0
1
1
0
0
1
1

Q
0
1
0
1
0
1
0
1

Q+
0
1
0
0
1
1
1
0

TT for J-K

J-K FF/Latch
Q

J
CLK
19

Logic

CLK

Function is D JQ K Q
K

Q
Q

Q
Q

(C) Counter Design

A counter is a special case of an FSM that cycles through its states
on receiving triggering clock pluses.
It does not have any external data I/Ps.
Reset

100

E
A

000

No external I/Ps
D

011

Counter O/P

Logic

Next State
bits

001

010

FFs

n
CLK

The states need to be encoded by binary bits.

20

State Transition Diagram and Table for a 3-bit Binary Up-Counter

Reset

Synthesis (3-Bit Up Counter)

000

Input
Present State

111

001

110

010

101

011

100

C
0
0
0
0
1
1
1
1

(a) State Transition

Diagram

FF Excitation Table Revisited

21

Q
0
0
1
1

Q+
0
1
0
1

R
x
0
1
0

S
0
1
0
x

J
0
1
x
x

K
x
x
1
0

T
0
1
1
0

D
0
1
0
1

B
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

Output
Next State

C+ B+ A+
0 0
1
0 1
0
0 1
1
1 0
0
1 0
1
1 1
0
1 1
1
0 0
0

Toggle Flip-Flop
Inputs

TC TB TA
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
(b) State Transition Table (What next state
will be given the
current state.)

Excitation table for R-S, J-K, T, and D Flip-Flops

From excitation table for FF inputs, get K-map for the FF inputs.
CB
00 01 11 10

A
0
1

1
1

1
1

1
1

1
1

TA=1

CB
00 01 11 10
A
0 0 0 0
0
1
0 1 1 0
TC=AB

CB
A

00 01 11 10
0
1

0
1

0
1

0
1

0
1

K-maps for Up-Counter Using Toggle

Flip-Flops.

TB=A

Obtain logic expr. for FF I/Ps (as functions of current state bits A,
B, C, --- A=QA, B=QB, C=QC) and realize the counter

22

Counters with More Complex Sequencing (Non-Consecutive Binary Outputs)

Present State

000

110

010

101

011
State Transition
Diagram

Implementation Using J-K FFs:

Present
State
C B A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
231 1 1

Next
State
+
C B+
0 1
x x
0 1
1 0
x x
1 1
0 0
x x

A+
0
x
1
1
x
0
0
x

JC
0
x
0
1
x
x
x
x

C
0
0
0
0
1
1
1
1

Remapped Next
State
KC JB KB
x
1 x
x
x x
x
x 0
x
x 1
x
x x
0
1 x
1
x 1
x
x x

B
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

Next State

C+ B+ A+
0 1
0
x x
x
0 1
1
1 0
1
x x
x
1 1
0
0 0
0
x x
x

State Transition Table

JA KA
0
x
x
x
1
x
x
0
x
x
x
1
0
x
x
x

State Transition Table and Remapped Next-State Functions

Q Q+ J K
0 0
0 x
0 1
1 x
1 0
x 1
1 1
x 0
Q JQ K Q
J-K Flip-Flop Excitation Table

Next State Functions

JC A

KC A

JB 1

KB A C
KA C

J A BC
CB
00
A
0 0
1 x
A

CB
0
1

11 10

0
1

x
x

x
x

00

01

11

10

1
x

x
x

x
x

x
1

CB
00
A
0 0
1 x
24

01

01

1
x

CB
A 00
JC

A
JB

11 10

0
x

x
x

JA

x
x

0
1

CB
0
1

01

x
x

11

10

1
x

x
0

KC

00

01

11

10

x
x

0
1

1
x

x
x

CB
00
A
0 x
1 x

01

x
0

Remapped K-Maps for J-K Implementation.

KB

11 10

x
x

x
1

KA

Actual Implementation ( Using J-K)

+

J
Q
CLK
K
Q

A
Count
signal

C
KB

A
C

J
Q
CLK
K
Q

B
KB

JA

J
Q
CLK
K
Q

JA

J-K Flip-Flop Implementation of 3 Bit Counter.

25

Registers

26

Registers
A flip-flop stores one bit of information
When a set of n flip-flops is used to store n bits of data, we refer
to these flip-flops as a register
Common register usages include
Holding a data value output from an arithmetic circuit
Holding a count value in a counter circuit
A common clock signal is typically used for
each flip-flop in a register

27

Shift register
A register that provides the ability
to shift its
contents by a single bit
May be to the right or left (or
possibly both)

28

Shift right register

Data is shifted to the
right in a serial fashion
using the In input
Positive edge triggered
Contents of each flip-flop
are transferred to the
next flip-flop at each
positive edge of the clock
Level sensitive devices
would not be
appropriate for this
circuit

29

Parallel-access shift register

Data transfer in computer systems is a common
function
If the transfer is n-bits at a time, the transfer is said to be
in
parallel
If the transfer is 1-bit at a time, the transfer is said to be
serial
To transfer data serially, data is loaded into a
register in parallel (in one clock cycle) and then
shifted out one bit at a time
Parallel-to-serial data conversion
If bits are received serially, after n clock cycles the
contents of a register can be accessed in parallel as
an n-bit item
Serial-to-parallel conversion
30

31

Counters
Special purpose arithmetic circuits used for
the purpose of counting
Design circuits that can increment or decrement a
count by 1
Counter circuits server many purposes
Count occurrences of certain events
Generate timing intervals for controlling various
tasks in a digital system
Track elapsed time between events
Often (but not always) built with T flip-flops
because the toggle feature is naturally suited
for implementing the counting operation

32

Up-counter with T flip-flops

33

34

35

36

37