Chapter 11 Laboratory

Experiment
11-0 Introduction to Experiments
11-1 Binary and Decimal Numbers
11-2 Digital Logic Gates
11-3 Simplification of Boolean Functions
11-4 Combinational Circuits

Chapter 11 Laboratory
Experiment
11-5 Code Converters
11-6 Design with Multiplexers

11-7 Adders and Subtractors

11-8 Flip-Flops
11-9 Sequential Circuits

Chapter 11 Laboratory
Experiment
11-10 Counters
11-11 Shift Register
11-12 Serial Addition
11-13 Memory Unit
11-14 Lamp Handball

Chapter 11 Laboratory
Experiment
11-15 Clock Pulse Generator
11-16 Parallel Adder and Accumulator

11-17 Binary Multiplier

11-18 Asynchronous Sequential Circuits
11-19 Verilog HDL Simulation Experiment

11-0 Introduction to Experiments

Experimental Equipment
A logic breadboard must have :
1.
2.
3.
4.

LED indicator lamp

Toggle switches to provide logic-1 and -0 signals.
Pulsers with pushbutton and debounce circuits
A clock-pulse generator with at least two
frequencies
5. A power supply of 5V.
6. Socket strips for mounting the ICs.
7. Solid hookup wire and a pair of wire strippers

11-0 Introduction to Experiments

Experimental Equipment
Additional equipment:
1. A dual-trace oscilloscope
2. A logic probe

3. A number of ICs.

11-0 Introduction to Experiments

Series 7400

11-0 Introduction to Experiments

Series 7400

11-0 Introduction to Experiments

Physical Layout

Ripple Counter IC 7493

Internal circuit
diagram
No connection

11-0 Introduction to Experiments

Ripple Counter IC 7493
When
drawing
Schematic
schematic
diagrams, the
diagram
IC number is written
insider the block.

All input terminals are

placed on the left of the
block.

11-0 Introduction to Experiments

Ripple Counter IC 7493
The letter symbols of the
signals are written inside the
block and the corresponding
pin numbers are written
along the external lines.
All output terminals
are placed on the
right of the block.

11-1 Binary and Decimal

Numbers
Objectives
1. Introduces the breadboard to the students.

2. Acquaints the students with the cathode-ray

oscilloscope.

Reference Material
Section 1-2 and 1-7

11-1 Binary and Decimal

Numbers
Binary Count
Connect the IC to
operate as a 4-bit
binary counter by
wiring the external
terminals, as shown in
the figure.

All connections should be made with the power

supply in the off position.

11-1 Binary and Decimal

Numbers
Oscilloscope Display
Using a dual-trace oscilloscope, connect the output
of the clock to one channel and the output of QA, to
the second channel, followed by QB, QC, QD.
Note that each flip-flop in turn divides its incoming
frequency by 2.

11-1 Binary and Decimal

Numbers
BCD Count
0
1

When both R1
and R2 are
equal to 1, all
four cells in the
counter clear to
0 irrespective of
the input pulse.

11-1 Binary and Decimal

Numbers
Output Pattern
Output QA produces a pattern of alternate 1's and
0's. Output QD produces a pattern of eight 0's
followed by two 1's.
Obtain the pattern for the other two outputs and
check all four patterns on the oscilloscope.
Connect the 7493 IC to count from 0000 to the
following final counts: 0101, 0111, 1011

11-2 Digital Logic Gates

Objectives:
Investigate the logic behavior of various IC gate:
7400 Quadruple 2-input NAND gates
7402 Quadruple 2-input NOR gates
7404 Hex inverters
7408 Quadruple 2-input AND gates
7432 Quadruple 2-input OR gates
7486 Quadruple 2-input XOR gates

11-2 Digital Logic Gates

Truth Table

Use one gate from each IC and obtain the

truth table of the gate.
Waveforms
For each gate, obtain the input-output
waveform by observing the oscilloscope.

11-2 Digital Logic Gates

Waveforms
Obtain the input-output waveform relationship
of the gate by observing the oscilloscope.

11-2 Digital Logic Gates

Propagation Delay

Connect all six inverters inside the 7404 IC

in cascade. The output will be the same as
the input except that it will be delayed.
Using the oscilloscope, determine the delay
from the input to the output of the sixth
inverter.

11-2 Digital Logic Gates

Universal NAND Gate

Using a single 7400 IC, connect a circuit that

produces
1.
2.
3.
4.
5.

An inverter
A 2-input AND
A 2-input OR
A 2-input NOR
A 2-input XOR

11-2 Digital Logic Gates

NAND Circuit

Using a single 7400 IC, construct a circuit

with NAND gates that implements the
Boolean function
F = AB + CD

11-3 Simplification of Boolean

Functions
Objectives:
Acquaints the students with the
relationship between a Boolean function
and the corresponding logic diagram.

Note:
If an input to a NAND gate is not used, it should
not be left open, instead, should be connected to
another input that is used.

11-3 Simplification of Boolean

Functions
Logic Diagram

11-3 Simplification of Boolean

Functions
Logic Diagram
implement the diagram and test the circuit by
obtaining its truth table.
Obtain the Boolean function of the circuit and
simplify it using the map method. Construct the
simplified circuit and test it.

11-3 Simplification of Boolean

Functions
Boolean Function
implement the two functions together using a
minimum number of NAND ICs.
F1 ( A,B,C,D ) = ( 0,1,4,5,8,9,10,12,13)
F2 ( A,B,C,D ) = ( 3,5,7,8,10,11,13,15 )

11-3 Simplification of Boolean

Functions
Complement
Plot the following Boolean function in a map:
F = A'D + BD + B'C + AB'D

Combine the 1's in the map to obtain the simplified

function for F in sum of products. Then combine
the 0's in the map to obtain the simplified function
for F' also in sum of products.

11-4 Combinational Circuits

Objectives
Design, construct and test four combinational
logic circuits.

Reference Material
Section 3-8 and 4-8

11-4 Combinational Circuits

Design Example:
Design a combinational circuit with four
inputsA,B,C, and Dand one output, F. F is
to be equal to 1 when A = 1 provide that B = 0, or
when B = 1 provided that either C or D is also
equal to 1. Otherwise, the output is to be equal
to 0.

11-4 Combinational Circuits

Majority Logic:
A majority logic is a digital circuit whose output
is equal to 1 if the majority of the inputs are 1's.
the output is 0 otherwise.

Parity Generator:
Design, construct, and test a circuit that
generate an even parity bit from four message
bits. Use XOR gates.

11-4 Combinational Circuits

Decoder
Implementation:
Implement and test
the combinational
circuit using a 74155
decoder IC and
external NAND gates.
F1 = xy +x'y'z'
F2 = x'y +xy'z'
F3 = xy +x'y'z

11-5 Code Converters

Objectives
Design and construct three combinational-circuit
converters.

Reference Material
Section 4-3

11-5 Code Converters

Gray Code to Binary
Design a combinational circuit that converts a
four-bit Gray code number into the equivalent
four-bit binary number. Implement the circuit with
exclusive-OR gates.

9's complement
Design a combinational circuit with four input
lines that represent a decimal digit in BCD and
four output lines that generate 9's complement of
the input digit.

11-5 Code Converters

Seven-Segment Display

The 7447 IC is
a BCD-toseven-segment
decoder/driver.

11-5 Code Converters

Seven-Segment Display

The 7730
seven-segment
display
contains the
seven LED
segments.

11-5 Code Converters

Seven-Segment Display

A 47 resistor
to VCC is needed
in order to
supply the
proper current
to the selected
LED segment.

11-6 Design with Multiplexers

Objectives
Design, construct a combinational circuit with
multiplexers.

Reference Material
Section 4-10

11-6 Design with Multiplexers

Multiplexer

The diagram and

function table of the
multiplexer

11-6 Design with Multiplexers

Design Specification
A small corporation has 10 shares of stock, and
each share entitles its owner to one vote at a
stockholder's meeting. The 10 shares of stock are
owned by four people as follows:
Mr. W: 1 share

Mr. X: 2 shares

Mr. Y: 3 shares

Mr. Z: 4 shares

Design a circuit that displays the total number of

shares that vote yes for each measure.

11-7 Adders and Subtractors

Objectives
Design, construct and test various adder and
subtractor circuits.

Reference Material
Section 4-3, 4-7 and 4-13

11-7 Adders and Subtractors

Half Adder
Design, construct, and test a half-adder circuit
using one XOR gate and two NAND gates.

Full Adder
Design, construct, and test a full-adder circuit
using two ICs, 7486 and 7400.

11-7 Adders and Subtractors

Parallel Adder
IC type 7483 is a 4-bit
binary parallel adder. Test it
by connecting the four A
inputs to a fixed binary
number such as 1001 and
the B inputs and input carry
to five toggle switches.

11-7 Adders and Subtractors

Adder-Subtractor
The subtraction
of two binary
numbers can be
done by taking
the 2's
complement of
the subtrahend
and adding it to
the minuend.

11-7 Adders and Subtractors

Adder-Subtractor
When M=0, the
bits of input B
keep unchanged.
The addition is
performed.

11-7 Adders and Subtractors

Adder-Subtractor
When M=1, the
XOR gates
complement the
bits of input B,
and C0 is equal
to 1. The
subtraction is
performed.

11-7 Adders and Subtractors

Magnitude Comparator

If S=0, A=B
If C4=1, A >= B
If C4=0, A < B
If C4=1 and
S<>0, A >B

11-8 Flip-Flops
Objectives
Construct, test and investigate the operation of
various latches and flip-flops.

Reference Material
Section 5-2 and 5-3

11-8 Flip-Flops
SR Latch

Construct an SR latch with two cross-coupled

NAND gates. Obtain the function table of the circuit.

11-8 Flip-Flops
Master-Slave Flip-Flops

Construct a Master-Slave Flip-Flops using two D

latches and an inverter.

11-8 Flip-Flops
Master-Slave Flip-Flops
Observe the waveform of the clock and the master
and slave outputs.
Verify that the delay between the master and the
slave outputs is equal to the positive half of the clock
cycle.
Obtain a timing diagram

11-8 Flip-Flops
Edge-Triggered Flip-Flops
Verify that the
output does not
change when the
clock input is logic-1,
when the clock goes
through a negative
transition, or when it
is logic-0.

11-8 Flip-Flops
Edge-Triggered Flip-Flops
Using a dual-trace
oscilloscope, observe
and record the
timing relationship
between the input
clock and output Q.

11-8 Flip-Flops
IC Flip-Flops
IC type 7476
consists of two JK
master-slave flipflops with preset
and clear.
Investigate the
operation of one
7476 flip-flop and
verify its function
table.

11-8 Flip-Flops
IC Flip-Flops
IC type 7474
consists of two D
positive-edgetriggered flip-flops
with preset and
clear.
Investigate the
operation of the
flip-flop and verify
its function table.

11-9 Sequential Circuits

Objectives
Design, construct and test synchronous sequential
circuits.

Reference Material
Section 5-7

11-9 Sequential Circuits

Up-Down Counter with Enable
Design, construct and test a 2-bit counter that
counts up or down.
If E = 0, the counter is disabled and remains at its
present count.
If E = 1, the counter is enabled. When x = 1 , the
circuit counts up. When x = 0, the circuit counts
down.

11-9 Sequential Circuits

State Diagram
Design, construct and test a
sequential circuit whose state
diagram is shown in the figure.

Verify the state transition and

output by testing the circuit.

11-9 Sequential Circuits

Design of Counter
Design, construct and test a counter that goes
through the following sequence:
0,1,2,3,6,7,10,11,12,13,14,15, and back to 0 to
repeat.
The counter must be self-starting. Verification is
done by initializing the circuit to each unused state
by means of the preset and clear inputs and then
applying pulse to see whether the counter reaches
one of the valid states.

11-10 Counters
Objectives
Construct and test various ripple and
synchronous counter circuits.

Reference Material
Section 6-3 and 6-4

11-10 Counters
Ripple Counter
Construct a 4-bit binary ripple counter using
two 7476 ICs. Modify the counter so it will
count down instead of up. Check that each
input pulse decrements the counter by 1.

Synchronous Counter
Construct a 4-bit binary counter and check its
operation. Using two 7476 ICs and one 7408
IC.

11-10 Counters
Decimal Counter
Design a synchronous BCD counter that counts
from 0000 to 1001. Using two 7476 ICs and one
7408 IC.

Binary Counter With Parallel Load

IC type 74161 is a 4-bit synchronous binary
counter with parallel load and asynchronous
clear.

11-10 Counters
Binary Counter With Parallel Load
Two counter-enable
input called P and T.
Both must be equal to 1
for the counter to
operate.

11-10 Counters
Binary Counter With Parallel Load

11-11 Shift Register

Objectives
Investigate the operation of shift registers.

Reference Material
Section 6-2

11-11 Shift Register

IC Shift Register

11-11 Shift Register

IC Shift Register

11-11 Shift Register

Ring Counter
A ring counter is a circular shift register with the
signal with the signal from the serial output QD
going into the serial input. Connect the J and K'
input together to form the input.
Verify by observing the state sequence after each
shift.

11-11 Shift Register

Feedback Shift Register
A feedback shift register is a shift register whose
serial input is connected to some function of
selected register outputs.

Connect a feedback shift register whose serial

input is the exclusive-OR of output QC and QD,
then verify it.

11-11 Shift Register

Bidirectional Shift Register
The 74195 IC can shift only right from QA toward
QD. Convert the register to a bidirectional shift
register by using the load mode to obtain a shift
left operation.

Connecting the output of each flip-flop to the input

of the flip-flop on its left and using the load mode
of the SH/LD input as a shift register control.

11-11 Shift Register

Bidirectional Shift
Register With
Parallel Load

11-12 Serial Addition

Serial Adder

Base on
this figure

11-12 Serial Addition

Serial Adder
Design and construct a 4bit serial adder using
the following ICs: 74195, 7408,7486 and 7476.

Testing the Adder

To test the serial adder, perform the binary
addition 5+6+15=26.

Check that the value in A is 1010 and that the

carry flip-flop is set.

11-12 Serial Addition

Serial Adder-Subtractor
Using the other two XOR gates from the 7486,
convert the serial adder to a serial addersubtractor with a mode control M.
When M = 0, the circuit adds A+B;
When M = 1, the circuit subtractor A-B.

11-12 Serial Addition

Testing the Adder-Subtractor
To test the adder part , perform the binary
addition 5 + 6 + 15 = 26.
To test the subtractor part , perform the binary
addition 15 - 4 - 5 - 13=26.

11-13 Memory Unit

Objectives
Investigate the behavior of a random-access
memory (RAM) unit and its storage capability.

Reference Material
Section 7-2, 7-3 and 7-5

11-13 Memory Unit

IC RAM
The least
significant bit of
the address is A0
and the most
significant bit is A3

11-13 Memory Unit

IC RAM
The chip select (CS)
input must be
equal to 0 to
enable the memory.

11-13 Memory Unit

IC RAM
The write
operation is
performed when
WE =0

11-13 Memory Unit

Testing the RAM
The RAM can be tested after making the following
connection:
connect the address inputs to a binary counter
using the 7493 IC
connect the four data inputs to toggle switches and
the data outputs to four 7404 inverters.

Connect input CS to ground and WE to a toggle

switch.

11-13 Memory Unit

ROM Simulator
A ROM simulator is obtained from a RAM when
operated in the read mode only.

Memory Expansion
use the CS inputs to select between the two ICs.
Test the circuit by adding a 3-bit number to a 2-bit
number to produce a 4-bit sum.

11-14 Lamp Handball

Objectives
Construct an electronic game of handball using a
single light to simulate the moving ball.

Reference Material
Section 6-2

11-14 Lamp Handball

IC Type 74194
This is a 4-bit
bidirectional shift
register with parallel
load.

11-14 Lamp Handball

Logic Diagram
Analyze the logic
diagram to ensure that
you understand how the
circuit operates.

11-15 Clock Pulse Generator

Objectives
Use an IC timer unit and connect it to produce
clock pulses at a given frequency.

Reference Material
Section 10-2

11-15 Clock Pulse Generator

IC Timer

2/3 VCC

1/3 VCC

11-15 Clock Pulse Generator

IC Timer
When the
threshold input
at pin 6 goes
above 3.3V, the
upper
comparator
resets the flipflop and the
output goes low
to about 0V.

11-15 Clock Pulse Generator

IC Timer
When the
trigger input at
pin 2 goes
below 1.7V, the
lower
comparator
sets the flipflop and the
output goes
high to about
5V.

11-15 Clock Pulse Generator

Circuit
Operation

tH=0.693(RA+RB)C
tL=0.693RBC

11-15 Clock Pulse Generator

Clock-Pulse Generator
Connect the circuit and check the output in the
oscilloscope.
observe the output across the capacitor C and
record its two levels to verify that they are
between the trigger and threshold value.
observe the waveform in collector of the
transistor at pin 7.

11-16 Parallel Adder and

Accumulator
Objectives
Construct a 4-bit parallel adder whose sum can be
loaded into a register.

Reference Material
Section 10-2

11-16 Parallel Adder and

Accumulator
Requirement
According to the
block diagram,
draw a detailed
diagram showing all
wiring between the
ICs.
Design a test
procedure to verify
the result of the
circuit.

11-17 Binary Multiplier

Objectives
Design and construct a circuit that multiplies two
4-bit unsigned numbers to produce an 8-bit
product.

Reference Material
Section 8-6

11-17 Binary Multiplier

Requirement
According to the
datapath block
diagram and
control state
diagram, design the
circuit by drawing
a detailed diagram
showing all wiring
between the ICs.

11-17 Binary Multiplier

Requirement
Design a test
procedure to
verify the result
of the circuit.

11-18 Asynchronous Sequential

Circuits
Objectives
Analyze and design asynchronous sequential
circuits.

Reference Material
Section 9-8

11-18 Asynchronous Sequential

Circuits
Analysis
Analyze the circuit
by deriving the
transition table
and output map of
the circuit.

11-18 Asynchronous Sequential

Circuits
Design
Design, construct, and test a D-type flip-flop that
triggers on both the positive and the negative
transition of the clock. The circuit has two inputsD
and Cand a single output, Q.
The value of D at the time C change from 0 to 1
becomes the flip-flop output. The output remains
unchanged as long as C=1.
The output is again updated to the value of D when C
changes from 1 to 0. The output remains unchanged
as long as C=0.

11-19 Verilog HDL Simulation

Experiment
Objectives
Acquaints the students with Verilog HDL and its
simulation.

Supplement to experiment 2
Compile the circuit described in HDL Example 33 and run the simulator to verify the waveform.

11-19 Verilog HDL Simulation

Experiment
Supplement to experiment 2
Assign the following delay to the Exclusive-OR
circuit shown in the figure: 10ns for an inverter,
20ns for an AND gate, and 30ns for an OR gate.
Then verify the waveform.

11-19 Verilog HDL Simulation

Experiment
Supplement to experiment 4
HDL Example 4-10 (section 4-11) demonstrates
the procedure for obtaining the truth table of a
combinational circuit by simulating it.
In order to get acquainted with the procedure,
compile and simulate HDL Example 4-10 and
check the output truth table.

11-19 Verilog HDL Simulation

Experiment
Supplement to experiment 5,7,8,9
Requirement:
write an HDL description of the corresponding
circuit
write a test bench to simulate and verify.

11-19 Verilog HDL Simulation

Experiment
Supplement to experiment 5, 7, 8, 9,
10, 11, 13, 14, 16, 17
Requirement:
write an HDL description of the corresponding
circuit
write a test bench to simulate and verify.