DESIGN AND IMPLEMENTATION OF UART SERIAL COMMUNICATION

MODULE
BY
USING VERILOG
By
Ramkrishna Naidu Y
(Reg.no:312232940011)
Under the guidance of

MR P jagan mohan m.tEch, assistant professor

Department of E.C.E
Sanketika Vidya Parishad Engineering College

OVER VIEW

Abstract

Introduction

Implementation of UART

UART Transmitter

UART Receiver

UART Baud rate generator

Results

Conclusion

References

ABSTRACT

UART(universal asynchronous receiver and transmitter) is a kind serial communication

protocol.

It includes three modules which is baud rate generator , transmitter and receiver.

Universal asynchronous receiver and transmitter takes bytes of data and transmits bit
by bit in sequential fashion.

Mostly UART is used for short distance, low speed, low-cost data exchange between
computer and peripherals.

INTRODUCTION

UART allows full duplex communication in serial link , thus has been widely used in data
communication and control systems.

Basic UART communication needs only two signal lines (RXD, TXD) to complete full
duplex data communication.

TXD is the transmitter side the output of the UART.

RXD is the receiver side the input of the UART.

INTRODUCTION

There are two states in the signal line , using logic 1 (high), logic 0 (low) to distinguish
respectively.

When the transmitter is idle , the data line is in the high logic state.

Otherwise when a word is given to the UART for asynchronous transmissions , a bit called
start bit is added to the beginning of each word that is to be transmitted.

The start bit used to alert the receiver that a word of a data is about to sent.

INTRODUCTION

After the start bit the individual data bits of the word are sent, with the least significant
bit (LSB) being sent first.

Each bit in the transmission is transmitted for exactly same amount of time as all of the
other bits.

When the entire data word has been sent , the transmitter may add a parity bit which
transmitter generates.

The parity bit used by the receiver to perform the simple error check.

INTRODUCTION

Receiver look for a stop bit after complete data transmission. If stop bit does not appear
when it is supposed to be UART will report framing error to the host.

The usual cause of a framing error is sender and receiver will not run at same speed or
signal interruption.
UART frame format:

IMPLEMENTATION OF UART

The UART serial communication module divided in to three sub modules Baud rate
generator
1.UART transmitter
2.UART receiver
3. Baud rate generator

The baud rate generator is used to produce the local clock signal which is higher than the
baud rate to control the receiver and transmitter.

The UART receiver module is used to receive the serial signals at RXD and convert them in
to parallel data.

IMPLEMENTATION OF UART

The UART transmitter module converts the bits in to serial according to the basic format
and transmits those bits through TXD.

UART MODULE BLOCK:

IMPLEMENTATION OF UART
UART TOP MODULE RTL SCHEMATIC:

UART TRANSMISSION

The function of a transmit module is to convert the sending 8-bit parallel data in to serial
data.

Adds start bit to the at the head of the data and parity, stop bit at the end of the data.

When UART transmit module reset by reset signal the transmit module immediately enters
the ready state to send.

The order follows the 1 start bit and 8 bit data and 1 parity bit, 1 stop bit.

UART RECEIVER
SYSTEM -CLK
DATA_H
SYSTEM RST

UART
RECEIVET

DATA_H

During the UART reception the serial data and receiving clock are asynchronous. So it is very
important to correctly determine the start bit of a frame data.

The receiver module receives the data from RXD pin , RXD jumps into logic 0 from logic 1 can
be regarded as the beginning of a data frame.

When the UART module is reset, it has been waiting the RXD level to jump.

The start bit is identified by detecting RXD level changes from high to low.

BAUD RATE GENERATOR

Baud rate generator is actually a frequency divider, this is calculated according to a

given system clock frequency.

the purpose of this baud rate generator is to precisely sample the asynchronous serial
data at the receiver.

Assume that the system clock is 32 MHz, baud rate is 9600bps, and then the output clock
frequency of baud rate generator should be 16*9600Hz.

there fore frequency coefficient (M) would be

M=32MHz/16*9600Hz=208

RESULTS
Simulation results for UART:

RESULTS
UART RTL SCHEMATIC:

RESULTS

UART technology schematic:

CONCLUSION

UART is a kind of a serial communication protocol mostly used for short-distances ,

low-speed, low-cost data exchange between a computer and peripherals.

UARTS are now commonly included in microcontrollers.

It provides the computer with RS-232 data-terminal-equipment(DTE) interface so that it can

talk to and exchange data with modems and other serial devise.

Serial transmission is commonly used with modems.

REFERENCES

Zou,Jie Yang,Jianning Design and Realization of UART Controller

Based on FPGA

Liakot Ali Roslina Sidek Ishak Aris Alauddin Mohd. Ali

Bambang Sunaryo Suparjo. Design of a micro - UART for SoC
application [J].In: Computers and Electrical Engineering 30 (2004) 257
268.

HU Hua, BAI Feng-e. Design and Simulation of UART Serial

Communication Module Based on Verilog -HDL[J]. J ISUANJ I YU
XIANDA IHUA 2008 Vol. 8

Frank Durda Serial and UART Tutorial. uhclem@FreeBSD.org

THANK YOU