CMOS Design

Susanta Sen
Institute of Radio Physics and Electronics
University of Calcutta

Spec2Layout, 2010

Review of
MOS Transistor

Spec2Layout, 2010

The MOS Transistor

Spec2Layout, 2010

MOS Transistor

Depletion

Spec2Layout, 2010

Inversion

MOS Transistor (contd.)

VG

ID

Vt
VDS

Channel Pinches off Current Saturates

Saturation Current increases with VG
Threshold Voltage Vt Device Turns ON
MOS can be used as SWITCH
Spec2Layout, 2010

MOS as SWITCH
Designing Logic Circuits
Logic 0 = 0V : Logic 1 = VDD
n-MOS : VG Vt OFF : VG = VDD ON
VDD

p-MOS: Negative VGS required

Connect Source to VDD

VG0 to VDD

Gate Voltage Negative w.r.t. Channel

VG VDD |Vt| OFF : VG = 0 ON

Spec2Layout, 2010

n-MOS SWITCH
Transferring Logic 1 (VDD):

Transistor
OFF

VDD

Vin = VDD

Vt

Vo
VDD

Source
Impedance
High

Weak 1
t

Transferring Logic 0 (0 V):

VDD
Vin = 0 V
Vo
VDD

Transistor
ON

t
Spec2Layout, 2010

Source
Impedance
Low
Strong 0
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p MOS Switch
Transferring Logic 1 (VDD):
VDD

VDD

0V

Strong 1

Vo

Transferring Logic 0 (0 V):

VDD

0V

Weak 0

Vo
0V

Vt
t
Spec2Layout, 2010

MOS Circuit Design

Digital Logic

Switching Theory
Revisited
Spec2Layout, 2010

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Review of Switching Theory

Switches in Series
C

F = C iff (A and B)

Switches in Parallel
A

F = C iff (A or B)

B
Spec2Layout, 2010

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Using n-MOS Switch

Constraint : C = 0
Series Connection
F = 0 when (A . B) is TRUE

C = 0

A nand B

Parallel Connection
A

F = 0 when (A or B) is TRUE

C = 0

A nor B
B
Spec2Layout, 2010

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Using p-MOS Switch

Constraint : C = 1
Series Connection
C = 1

F = 1 when ( A . B) is TRUE
A+B
A

Parallel Connection
A

C = 1

F = 1 when ( A + B) is TRUE
A.B
B
Spec2Layout, 2010

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CMOS Logic Design

Pull UP Network
Build using p-MOS
Turns ON when Function is TRUE

Pull DOWN Network

Build using n-MOS
Turns ON when Function is FALSE

Operationally Complement
Topologically Dual
Spec2Layout, 2010

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CMOS Logic (contd.)

A

B
F

F
A

B
B

NOR Gate

NAND Gate
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CMOS Design Example

Consider the Function
f = A . (B + C)
A
C

f = [A . (B + C)] is true

F
B

Design the
Pull Down
Network first

Pull Up

The Pull Down Network connects

f to ground when

Connect Ground
Spec2Layout, 2010

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Assignments
1. F = A.B + C

2. F = (A + B).(C + D)
3. F = A + B.C

4. F = A + B.C
5. F = A.C + B.C

6. F = A B
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When the Signal Changes!

The CMOS Inverter

VDD
VDD
Vo

Vo
Logic 1
Output

Logic 0
Output
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Steady State
Input-Output Characteristics

Spec2Layout, 2010

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MOS Amplifier
VO = VDD ID.RL

Load Line

ID
V
DD

VG

I
RL

VDD

VDS
V
DD

VO
Vi
(=VG)

VO

Vi
Spec2Layout, 2010

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Non Linear Load

LOAD LINE

VO= VDD Vdiode

VDD
ID

VO
Vi

VDD VDS
VDD

VO
Vi
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Non Linear Load (contd.)

VDD

ID
VB
VO
Vi
VDD

VDD

VDS

VO
Vi
Spec2Layout, 2010

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Amplifier
or Inverter
The CMOS
Inverter?

ID

Vi

VO

VDD

VDS

VDD

Gate Bias of PMOS changes with

Input Voltage
Spec2Layout, 2010

VO
Vi

VDD
27

A Closer Look
VO= f (Vi)
VOH

Gain = VO/Vi

In presence of Noise

VOn = f (Vi + vn)

= f (Vi) + vn(VO/Vi) + vn2(2VO/Vi2)+

VO

noisy_output = noiseless_output +
noise x gain + higher order terms
VOL
ViL

ViH

Vi

Digital Noise immunity

Analog High Gain

Spec2Layout, 2010

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Noise Margins
VOH

VO

Undefined
Region

0
VOL
ViL

ViH

VOH

ViL
VOL

ViH

NML = VIL VOL

Vi

Digital Noise immunity

Spec2Layout, 2010

NMH = VOH VIH

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Tuning the Characteristics

ID = Cox[VGS Vt]2 (W/L)
ID
Vi

VO
VDD

VDS

VDD

Make the n-MOS wider

It conducts more current
Best Noise Margin
When Vi = Voat VDD/2

Spec2Layout, 2010

VO
Vi

VDD
30

Attention to Speed
p-MOS slower than n-MOS
Hole mobility < Electron mobility
Pull-UP Higher Resistance
Rise time longer

Make p-MOS wider

Resistance W/L Ratio
Wp = 2. Wn

Spec2Layout, 2010

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More Attention to Speed

Widen transistors connected in Series
Increases Input Capacitance

Avoid Series connection of p-MOS

Prefer NAND over NOR

Avoid Complex Gates

Limit Fan-in to 4

Multi-level Synthesis required

Spec2Layout, 2010

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Power Dissipation
No Static Dissipation
Except leakage current
Dynamic Dissipation
Charging and discharging load capacitor
Direct Path Dissipation
During switching

Spec2Layout, 2010

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Dynamic Dissipation (0 1)
IL= CL.dVo/dt
IL

Edrawn= VDDILdt = VDDCLdVo = CLVDD2

Vo

Ediss(in Rp) = (VDD- Vo) ILdt

= CL(VDD- Vo)dVo = CLVDD2
P-MOS On
N-MOS Off

Estored (in CL)= CLVDD2

Spec2Layout, 2010

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Dynamic Dissipation (1 0)

Vo

Ediss(in Rn) = Estored= CLVDD2

Spec2Layout, 2010

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Dynamic Dissipation
2

Ediss(01) = CLVDD

Ediss(10) = CLVDD

Edyn per clock cycle = CLVDD2

2

Pdyn= Ediss per sec = f.CL.VDD

VDD=2.5V CL=15 fF/gate f = 500 MHz

Pdyn= 50 W/gate
1 million gate chip 50 W dissipation on chip
Spec2Layout, 2010

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Silver Lining
Not all gates change state on each
clock cycle
If be the transition probability at the
gate output
Pdyn = f.CL.VDD2

Estimation of is important
Spec2Layout, 2010

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Direct Path Dissipation

lin
lin
2
2
~
Edp/cycle=2.(VDD.Ipk.tsc) = VDD.tsc/( Rn + Rp ) = Cdp.VDD

tsc= ts.(VDD 2Vth)/VDD = (tr /0.8).(VDD 2Vth)/VDD

Spec2Layout, 2010

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CMOS Logic Circuit

Advantages
Low Power Dissipation in Steady State
Either Pull-up OR Pull-down ON
No direct path current from VDD Gnd
Only Static Dissipation (Leakage)
Significant at high circuit density

High Packing Density

Large Circuits on single chip
Spec2Layout, 2010

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Low Power Design Considerations

Switching Loss:

Minimize CL Technology
Minimize activity () Circuit + Algorithm
Stop inactive circuit Clock gating
Reduce VDD Speed suffers
Scaling + Parrallel/Pipeline architecture

Static Loss
Modify threshold Voltage Multi-threshold
Idle mode control Switch off Power
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More About Logic Design

Handling Complex Circuits
Speed Requirement Fan-in 4

Break-up Design into smaller units

Multi-level Synthesis

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Spec2Layout, 2010

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