Semiconductor Memory Design

Design of smaller, cost effective, power efficient and faster

memories for portable and non portable devices comes under
semiconductor memory design.

Applications of Memory

Classification of memories
Read write Memory
(RWM)

Non-volatile RWM
(NVRWM)

Read only memory

(ROM)

Random
Access

Non Random
Access

SRAM

FIFO

EPROM (Electrically
programmable ROM)

Mask programmed

DRAM

LIFO

EEPROM (Electrically
erasable Programmable
ROM)

PROM (Programmable
ROM)

Shift
Register(SR)

FLASH

Content
Addressable
(CAM)

Read write memory

Can be read as well as written easily unlike ROM.

Is of two types: random access and non random access.

Access time for data doesnt not depend on its location in

random access memory.

Access time for data depends on its location in non-random
access memory.

Types of Random access RWM

SRAM

Volatile.
Fast.
Expensive.
Low power.
Low density and more space requirement.

DRAM
Cheap
High Density and less space requirement.
Slower
Requires refreshing
High power requirement.

TYPES OF NON RANDOM

ACCESS RWM
FIFO (First in first out)
Stores data elements in form of queue.
First input element goes out first.
Used in buffers.

LIFO (Last in first out)

Last element goes out first.

Used in register based memory applications.

Shift register
Uses shift registers to hold data

TYPES OF NON RANDOM

ACCESS RWM
CAM (Content addressable memory)
Compares contents of input data with contents of CAM
block and generates data.
Faster as compared to RAM.

Types of NVRWM
EPROM

Holds content until exposed by UV light.

Erase is slow ( seconds to several minutes).
Programming is slow.
Limited number of programming cycles- about 1000.
Very dense.

EEPROM

Holds content until erased electrically.

Limited number of programming cycles- 10 to 100000.
Erase is fast.
No problems due to accidental exposure to UV light.

Types of NVRWM
FLASH memory
Combines features of EPROM and EEPROM.
Erasure performed using Fowler-Nordheim tunneling.
Particular memory location can be erased .
No need to erase entire data.
Faster access time.

TYPES OF ROM
Mask programmed ROM
Programmed by integrated circuits manufacturers.
More compact than any other semiconductor memory.
Cannot be reprogrammed by user.
Cannot be modified at later stage, once manufactured.
PROM
One time programmable.
Data is programmed after manufacturing.
Store permanent data like microcode.
Cannot be reprogrammed by user.

SRAM architecture
Sub-blocks of typical SRAM architecture.
Column Drivercontains circuitry required for reading from

and writing to the Bitcell Array.

Bitcell Arrayconsists of a two-dimensional arrangement of
bitcells, each of which stores one bit worth of data. A bitcell
row comprises a word.
Sense Amplifiercommonly called a sense amp, it contains
analog circuitry for reading the contents of a selected bitcell
row.
Address Decoderdecodes address of words from a specified
memory address.

SRAM Architecture

SRAM cell array details

For write operation, column bit lines are driven differentially
(0 on one, 1 on the other).Values overwrites cell state.
For read operation, column bit lines are equalized (set to same
voltage), then released. Cell pulls down one bit line or the other.

Commonly used SRAM cells

The 4T cell (four NMOS transistors plus two poly load

resistors)
The 6T cell (six transistorsfour NMOS transistors plus two
PMOS transistors)
The TFT cell (four NMOS transistors plus two loads called
TFTs)

6T SRAM CELL
Write operation.

6T SRAM cell
Read operation

6T SRAM cell
Advantages
High speed and noise immunity.
Low standby current.
Disadvantages
Large cell size.

4T SRAM cell

Uses poly load resistors instead of PMOS as load.

Smaller in size compared to 6T SRAM cell.

Has high standby current.

Sensitive to noise.

TFT Cell

Designed to overcome limitation of high standby current of 4T

SRAM cell.
Uses PMOS transistor formed by thin film transistor (TFT)
technology.
Difficult to fabricate.

Challenges in SRAM design

Reduction in cell size.

Reduction in sub-threshold leakage current.

Increased voltage swing.
Low power supply requirements.
Reduction in power dissipation.

Emerging memory technologies

SONOS

stands for silicon oxide nitride oxide silicon.

Non-volatile memory.
Uses silicon nitride as gate material instead of poly
silicon.
Requires lower programming voltages.
Has high endurance.

FeRAM

Stands for ferroelectric RAM.

Emerging memory technologies

FeRAM ( contd)

Lower power usage.

Faster programming time.
Greater endurance
Uses ferroelectric gate cell instead of poly silicon.

3D-NVRAM

Non volatile memory.

Uses multi-stacked memory array.
Has very high density.

Emerging memory technologies

PCRAM

Stands for phase change RAM.

Stores data into chalcogenide glasses.

ZRAM

Stands for zero capacitor RAM.

Uses floating body effect of SOI technology to store data.
High read and write speed.
Highly scalable( upto 32nm) and consumes less power.

Emerging memory technologies

TRAM (contd)

High density and high speed.

Highly scalable( upto 22nm).

ReRAM

Stands for resistive random access memory.

Stores data as change in electrical resistance.
High endurance and smaller cells.

Emerging memory technologies

MRAM

Stands for magnetoresistive RAM.

Uses ferromagnetic plates to hold data.

TRAM

Stands for thyristor RAM.

Uses negative differential resistance.

References
Tomohiko nakamura, 2012, Technology strategy for the

semiconductor memory market,MIT.

http://www.ece.unm.edu/~jimp/vlsi/slides/chap8_2.html.
http://www.radioelectronics.com/info/data/semicond/memory/
different-types-semiconductor-memory.php.
M. Qazi, M. E. Sinangil, A. P. Chandrakasan, Challenges and
Directions for Low-Voltage SRAM IEEE Design & Test of
Computers, January/February 2011.
http://www.ee.ncu.edu.tw/~jfli/vlsi2/lecture/ch03.pdf.

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