Paul Coroneos

Introduction
High-speed electrical links are an essential part of how

various electronics communicate with one another.

Applications include:
Internet routers
Interconnects between mutli-core processors
Designers simply cannot just lay traces on a board or
transmit a signal wirelessly and expect their design to
operate at high speeds.
Special I/O circuitry is required.

Introduction
Topics touched on in this presentation include:
Serializers
Transmitters

PLLs
Receivers
Deserializers
Channels non-ideal effects
Modulation schemes

Serializer
IC packages can only have so many physical packages
Conflicts with size of packaging.
Want packages to become smaller as Moores law
evolves.
Use a serializer!
The serializer takes parallel data and combines it into

a single signal.
Done using a multiplexer in the transmitter circuit

Serializer
Typically done using tree-mux w/ 2:1 stages cascaded

(D flip flop).
Clock duty-cycle not a big concern
However, suffers from limited maximum data

Also consumes a TON of power. (~100mW)

As a result, half-rate is commonly used.

Also eliminates the need for the high speed clock and
flip-flops.
However, clock duty-cycle is an issue now.
CML drivers may also be used to speed up serializer,

but at cost of additional power consumption.

Serializer - Full versus Half

Clock
Clock distribution is also a concern
Controls speed and quality of transmitter.
Maximum clock frequency limited by the delay of the
buffers it must pass through.
~4Ghz in 90nm CMOS
May improve upon this by using CML buffers along

with common BW extensions techniques

ie shunt and series peaking

Transmitters
Variety of topologies!
Current-mode
Voltage-mode
Each has its own advantages and disadvantages
Current-mode drivers operate by steering a high

current between two differential outputs in order to

create a high voltage swing
Works on principle of Norton-equivalent parallel

termination.

Transmitters
Two varieties are push-pull and CML
Push-pull have:
Good PSRR
Suffer from headroom issues @ low VDDs
CML does not have this issue.
But also operates at half the swing.
Operates using Thevenin-equivalent series

termination
Common topologies are high and low swing.

Transmitters
Consist of NMOS and CMOS driver respectively
Current-mode drivers are most common
Suffer from significant power burning!!!
Therefore, voltage-mode drivers are VERY attractive to

designers
Consume as little as 25% of the power of a comparable

current-mode driver!

Push-Pull

CML Driver

Timing Circuit
Next important part about electrical link circuits is the

timing circuitry!
Clocks in the electrical link must be both highprecision and low noise to meet design challenges
PLL is circuit of choice to synthesize clock to serialize
the half-rate parallel input data.
PLL consists of a few components:
PFD/PD, Loop Filter, VCO, divider (integer or higher)
A diverse amount of topologies for these with all sorts
of advantages and disadvantages.

PLL
All of these components form negative feedback

system.

Phase-Frequency Detector
PFD compares the feedback signal from PLL to a

reference clock.
PFD then outputs a late and early error signal.
Different types include bang-bang and PFD
Bang-bang only convey late or early, more commonly

used in CDR
PFD gives how much the signal is late and early
This control signal is fed to the loop filter which then
controls two different current sources to charge and
discharge the loop filter capacitor.

Loop Filter
Control voltage from capacitor based on early and late

signal ultimately controls VCO.

Loop filter is used as a low pass filter in order the
extract the average of the late and early.
Capacitor sizing in the LF will determine whether it is
optimized for stability or jitter depending on needed
application

VCO
VCO in the case of high-speed electrical link

synthesizes the higher frequency signal depending on

the control voltage.
Two main types are ring and LC oscillator
Ring oscillators:
Easier to integrate
Have wide tuning range
Small area
Bad phase noise
Can generate multiple phase clocks for time-division

multiplexing applications.

VCO

LC Oscillator:
Larger area due to inductors
Superior phase noise performance
Tuning range is limited
The PLL must have low timing noise, otherwise the

phase noise may dominate the output clock.

Ring and LC Oscillator

Frequency Divider
Acts to step the output frequency of the VCO back

down to the original frequency so that it may be

compared to the reference in the PFD.
Many different topologies, including TSPC flip-flop
and CML latch.
Both have their advantages and disadvantages.
Both synchronous and asynchronous approaches used,
depending on how much jitter is acceptable in the
circuit.
Dual Modulus Prescalers used to generate division
ratios other than 2.

Dual Modulus Prescaler

Clock Data Recovery Circuit

CDR controls timing on the receiver end.
Positions the clock in center of data eye-diagram
Also filters incoming signal jitter

PLLs can be utilized as CDR.

PD is used instead of PFD due to difficulty of created a
thin edge.
Width corresponds to dead zone
BW must also be small, meaning that rig osc. phase
noise will go largely unfiltered.

Clock Data Recovery Circuit

Dual-loop CDR is therefore a very attractive choice as

it also filters noise generated by the VCO.

CDR PDs compare phase noise between input data and
the recovered clock.
Most are non-linear due to difficulty of
implementation. (sign information only)

Channel non-ideal effects

As discussed previously, the speed of the electrical link

is most attenuated by high-frequency loss due to the

channel
Also due to impedance variations causing reflection
Crosstalk is another big issue!
The magnitude of this attenuation depends on the
length and quality of the channel.
Dispersion also is a factor.
Dispersion is high frequency loss due to skin effect
and dielectric loss.

Channel non-ideal effects

Channel non-ideal effects

Skin effect occurs because the electrons in the signal

current tend to propagate near the surface of the

conductor. This impacts the resistive loss proportional
to the square root of the frequency.

Er is relative permittiiviy, c is speed of light, and

tan(deltad) is the board materials loss tangent.

Channel non-ideal effects

Dielectric loss is caused when energy is absorbed

from the channel and turned into heat due to atom

rotation in the electric field
Due to time varying current inducing an electric law
(Maxwell and Faraday)
Proportional to frequency.

Channel non-ideal effects

These effects will interfere with adjacent bits in data

stream
Called ISI or intersymbol interference.
May close eye-diagram for received data!
Reflection is also an issue, and is caused by the signal
meeting varying impedance as it crosses the
transmission line.
Caused a time delayed version of the data signal to be

received at receiver

Mismatch and VIA stubs are also common culprits.

Channel non-ideal effects

Crosstalk is a growing issue.
Crosstalk occurs when two signal lines experience

capacitive and inductive coupling

longer the signal travels, the more crosstalk.
Can be NEXT, where aggressor signal energy reflects
onto victim or FEXT, where aggressor travels down
channel and overpowers victim on another chip.
Dangerous because energy created can exceed the
signal at speeds of 4GHz in 90nM CMOS.

Equalization
What can be done if channel non-ideals too large for

convention design?
Equalization!
Equalization can cancel ISI
Can be done using linear filters to flatten out overall

channel frequency response

Or non-linear filter that cancels specific cursors.

FIR filters quite common

Implemented on the transmitter side as pre-emphasis or
de-emphasis depending on what portion of response
you want to change (high-low)

Equalization
Predominantly done on transmitter side due to easy of

DAC design versus ADC.

Linear receiver side equalization also has its challenges
Crosstalk and high frequency noise may be amplified

too!
Delay block design can also be hard.

However advantages are enormous

Tap coefficients can be tuned for each channel (Nice!)
Linear receiver equalization can also be implemented

using a differential amplifier applying neutralization.

Equalization
However, this topology will suffer from a limited max

data rate.

Equalization
A final equalization considered if receiver-side

decision feedback equalization (DFE)

Directly subtracts ISI using negative feedback to taps.
Advantage of not amplifying those non-ideal effects
such as the high frequency loss and crosstalk.
Suffers drawback of noise
Noise may cause error in taps

Also cannot cancel pre-cursor ISI.

(Cant make a forward delay element!)

Modulation techniques
I would like to briefly touch on modulation
All signaling has been assumed to be binary thus far.
However, using PAM-4 doubles the bits per signal.
By doing so, twice as much data can be sent, increasing the

data rate of the circuit regardless of channel limitations!

However, voltage margin of 9.5dB must be considered
Rule of thumb is that if channel loss in binary is > 10dB,
PAM-4 can be utilized!
However, must consider non-ideal effects of PAM-4 (ie ISI
and jitter)

Modulation Techniques
Future is pointing to multi-tone signaling
Already used in DSL modems, high-speed electrical links

may be a new home.

Breaks up BW of the channel over a few frequency bands.
Helps reduce the per-band loss and avoid nulls (channel
impedance imperfections)
Requires a LOT of digital processing, and a fast ADC/
Also consumes a lot of power
Analog mixing techniques w/ integration filters along with
MIMO DFEs are in development to cancel band-to-band
interference.

Conclusion
This is a rough summary of current design issues and

proposed solution for high-speed links.

Lots of research needed to be done to continue to
meet increasing speed requirements.
Most gain will probably come from equalization
techniques.
Move to optical will help.
However, in short term, improving electrical will be
very important.
Thanks for listening!