Professional Documents
Culture Documents
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
Basic architecture
Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
UART
MIL-STD-1553B
SCSI
A very fast external bus standard that supports data transfer rates
of up to 400Mbps (in 1394a) and 800Mbps (in 1394b).
Can be used to connect up 63 external devices.
Defines 100, 200, and 400 Mbps devices and can support the
multiple speeds on a single bus, and flexible
Supports freeform daisy chaining and branching for peer-to-peer
implementations.
Is also hot pluggable (devices can be added and removed while
the bus is active).
Supports two types of data transfer: asynchronous and
isochronous.
Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
CPU
Basic structure
Fetch and execute cycle
Microcontrollers
Instruction forms
Core instructions
Addressing modes
RISC versus CISC
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Basic structure
Partial, stylized, internal structure of a typical CPU. The internal paths represent connections to the
internal bus structure. The connection to the system bus is shown on the right.
Copyright 2004 Dr. Phillip A. Laplante
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Microcontroller
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Instruction forms
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Instruction forms
0-address form
1-address form
2-address form
Stack machine
RPN calculators
JVM
3-address form
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Core instructions
horizontal-bit operation
vertical-bit operation
data movement
e.g. rotate left, rotate right, shift right, and shift left
Control
mathematical/special processing
other (processor specific)
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Addressing modes
immediate data
direct memory location
indirect memory location
register indirect
double indirect
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Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
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Memory
Memory technologies
Memory organization
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Memory technologies
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Memory technologies
Memory type
DRAM
SRAM
UVROM
Fusible link
PROM
EEPROM
Flash
Ferroelectric
RAM
Ferrite core
Typical access
time
50-100 ns
10 ns
50 ns
50 ns
Density
Typical applications
64 Mb
1 Mb
32 Mb
32 Mb
main memory
memory , cache, fast RAM
Code and data storage
Code and data storage
50-200 ns
20-30 ns (read)
1 s (write)
40 ns
1 Mb
64 Mb
64 Mb
various
10 ms
2 Kb or less
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Memory organization
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Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
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Input/Output
Memory mapped I/O versus
programmed I/O
Three basic I/O methods
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Programmed I/O
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Polling
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Interrupts
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Step 1: complete the currently executing instruction. Step 2: save the contents
of PC to interrupt return location i. Step 3: load the address held in interrupt
handler location i into the PC. Resume the fetch-execute cycle.
Copyright 2004 Dr. Phillip A. Laplante
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Interruptible instructions
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Watchdog timers
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Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
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Enhancing performance
Locality of reference
Cache
Pipelining
Coprocessors
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Locality of reference
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Cache
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Cache
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Pipelining
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Pipelining
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Pipelining
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Coprocessors
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Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
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ASICs
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PAL/PLA
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FPGAs
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Tranducers
Temperature sensors
Accelerometers
Gyroscopes
Position resolvers
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Temperature sensors
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Accelerometers
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Gyroscopes
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Position resolvers
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A/D converters
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D/A converters
Digital-to-analog conversion performs the
inverse function of A/D circuitry.
Converts a discrete quantity to a
continuous one.
D/A devices are used to allow the
computer to output analog voltages based
on the digital version stored internally.
Communication with D/A circuitry uses
one of the three input/output methods
discussed.
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Hardware considerations
Basic architecture
Hardware interfacing
CPU
Memory
I/O
Enhancing performance
Other special devices
Non von Neumann architectures
Copyright 2004 Dr. Phillip A. Laplante
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multiple instruction
stream
pipelined architectures
dataflow processors
VLIW processors
transputers
grid computers
hypercube processors
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