SPEED

SPACE
POWER
FUNCTIONALITY

Full Scaling ( Constant Field Scaling )

Quantity

Before Scaling

After Scaling

Channel length

L/S

Channel width

W/S

Gate oxide thickness

tox

tox/S

Junction depth

xj

xj/S

Power supply voltage

Vdd

Vdd/S

Threshold voltage

Vt

Vt/S

Doping Densities

Na

S*Na

Nd

S*Nd

Quantity

Before Scaling

After Scaling

Oxide
Capacitance
Drain Current
Power Dissipation
Power Density

Cox

S*Cox

Id
P

Id/S
P/S2

P/Area

P/Area

Constant Voltage Scaling

Quantity

Before Scaling

After Scaling

Channel Length

L/S

Channel Width

W/S

Gate oxide thickness

tox

tox/S

Junction depth

xj

xj/S

Lateral electric field

Ey

S*Ey

Supply Voltage

Vdd

Vdd

Threshold voltage

Vt

Vt

Doping Densities

Na

S2*Na

Nd

S2*Nd

Quantity
Oxide
Capacitance
Drain Current
Power
Dissipation
Power Density

Before Scaling
Cox

After Scaling
S*Cox

Id
P

S*Id
S*P

P/Area

S3* P/Area

Summary:
Constant

field scaling increases speed, reduces

size and reduces power consumption as well.
On

the other hand, constant voltage scaling

increases speed, reduces size but increases power
consumption.
Inspite

of this drawback, constant voltage scaling

is usually preferred because it is difficult to
provide multiple power supply voltages and to
necessitate
complicated
level
shifter
arrangements required in constant field scaling.

SHORT CHANNEL
EFFECTS

There are ten major short channel effects:

1. Velocity Saturation
2. Surface Scattering
3. Drain Induced Barrier Lowering (DIBL) &
Subthreshold Conductance
4. Gate Oxide Leakage
5. Gate Induced Drain Leakage (GIDL)
6. Lower Transconductance
7. Stress Induced Leakage Current (SILC)
8. Channel Length Modulation
9. Impact Ionization
10. Hot Electrons

Variation of drift velocities in Si and GaAs

with applied electric field
Velocity
saturation

Mobility: Drift velocity per unit electric field

11/27/2014

11

At low Ey, the electron drift velocity vd in the channel varies

linearly with the electric field intensity. However, as Ey
increases above 104 V/cm, the drift velocity tends to increase
slowly, and approaches a saturation value of vd = 107 cm/s
around Ey = 105 V/cm at 300 K.

As the field increases above 104 V/cm, optical phonons are

emitted alongside acoustic phonon.
Due to this, the drift velocity cannot increase above certain
level and it becomes saturated. So, the current eventually is
found lesser than the anticipated value.

As the channel length becomes smaller, due to the

lateral extension of the depletion layer into the channel
region, the longitudinal electric field component Ey
increases, and the surface mobility becomes fielddependent.

Since the carrier transport in a MOSFET is confined

within the narrow inversion layer, and the surface
scattering, that is the collisions suffered by the
electrons that are accelerated toward the interface by
Ex causes reduction of the mobility and the electrons
move with great difficulty parallel to the interface.
So, the average surface mobility becomes less as
compared to that of the bulk mobility and eventually it
affects the current.

The equation for source and drain junction

widths:

Current flows due to sustained surface inversion.

The current flow in the channel depends on

creating and sustaining an inversion layer on the
surface.
If the gate bias voltage is not sufficient to
invert the surface (Vgs<Vt), the carriers
(electrons) in the channel face a potential barrier
that blocks the flow.
Increasing the gate voltage reduces this
potential barrier and, eventually, allows the flow
of carriers under the influence of the channel
electric field.

In small-geometry MOSFETs, the potential barrier is

controlled by both the gate-to-source voltage Vgs and the
drain-to-source voltage Vds.
If the drain voltage is increased, the potential barrier in
the channel decreases, leading to drain-induced barrier
lowering (DIBL).
The reduction of the potential barrier eventually allows
electron flow between the source and the drain, even if
the gate-to-source voltage is lower than the threshold
voltage.
The channel current that flows under this conditions (Vgs<
Vt) is called the sub-threshold current.

Punch Through:

For large drain bias voltage, the depletion

region of drain extends towards source and
merges. This is called punch through.

Punch through can be minimized by:

1.
2.
3.
4.

Thinner oxide
Larger substrate doping
Shallower junctions
Longer channels

Increased gate-oxide leakage

The gate oxide, should be made as thin as possible to increase
the channel conductivity and performance when the transistor
is on and to reduce subthreshold leakage when the transistor
is off.
However, with very thin gate oxides the quantum mechanical
phenomenon of electron tunnelling occurs between the gate
and channel, leading to increased power consumption
Insulators that have a larger dielectric constant than silicon
dioxide (referred to as high-k dielectrics), such as group IV B
metal silicates e.g. hafnium and zirconium silicates and oxides
are being used to reduce the gate leakage from the 45
nanometre technology node onwards.

GATE INDUCED DRAIN LEAKAGE (GIDL)

Vgs<0, Vds>0
Higher supply voltage and thinner oxide increase GIDL.

The n+ drain region under the gate is be

depleted and even inverted. This causes field
crowding and the peak.
So field increase, resulting in avalanche
multiplication and band-to-band tunneling.

Thus minority carriers are emitted in the drain

region underneath the gate and leakage current
flows through the substrate.
Thinner oxide, higher Vdd enhances the electric
field and therefore increase GIDL.

GIDL increases with the increase in Vdb and Vdg.

LOWER TRANSCONDUCTANCE

The transconductance of the MOSFET decides its

gain and is proportional to hole or electron mobility.

As MOSFET size is reduced, the fields in the

channel increase and the dopant impurity levels
increase. Both changes reduce the carrier mobility,
and hence the transconductance.
Velocity saturation of the carriers, limiting the
current and the transconductance.

STRESS INDUCED LEAKAGE CURRENT

Stress Induced Leakage Current (SILC) is an increase in

the gate leakage current of a MOSFET, due to defects
created in the gate oxide during electrical stressing.
No SILC was observed for thinner films, while thicker
oxides shows large variation due to process induced
charging damage.
The effect of different gate poly-Si etching process in a
high density plasma system were also evaluated. Only the
gate that was etched with an abnormally high bias power
over etch process, and connected to large connection
antenna ratio shows SILC

Example: SILC increases as the contact antenna size

increases in 3.7nm and 5.2nm gate oxide

Channel Length Modulation

The pinch-off point moves toward the source as VDS

increases.
The length of the inversion-layer channel becomes
shorter with increasing VDS.
ID increases (slightly) with increasing VDS in the
saturation region of operation.

I D , sat

1
W
VGS VTH
nCox
2
L

2 1 VDS VD,sat

The effect of channel-length modulation is less for

a long-channel MOSFET than for a short-channel
MOSFET.

An example of an incoming electron impact ionizing to

produce a new electron-hole pair

Occurs especially in NMOS due to the high velocity of electrons in

presence of high longitudinal fields that can generate electron-hole (e-h)
pairs by impact ionization, that is, by impacting on silicon atoms and ionizing
them.
Normally, most of the electrons are attracted by the drain, while the holes
enter the substrate to form part of the parasitic substrate current.
Moreover, the region between the source and the drain can act like the
base of an npn transistor, with the source playing the role of the emitter
and the drain that of the collector. If the holes are collected by the
source, and the corresponding hole current creates a voltage drop in the
substrate material, the normally reversed-biased substrate-source pn
junction will conduct appreciably.
Then electrons can be injected from the source to the substrate, similar
to the injection of electrons from the emitter to the base. They can gain
enough energy as they travel toward the drain to create new e-h pairs.
The situation can get worst if some electrons generated due to high fields
escape the drain field to travel into the substrate, thereby affecting
other devices on a chip.

Due to high electric field

near the Si-SiO2 interface
electrons gain sufficient
energy
to
cross
the
interface potential barrier
and enter into the oxide
layer .

They are trapped causing

oxide
charging
which
accumulate with time.
This
causes
transistor
threshold shift and mobility
change effecting gates
control on drain current.

Extra threshold is proportional to the ratio of xdm to W. So, in

narrow channel there is increase in the threshold voltage.