Department of Technical Education

Andhra Pradesh
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Institute
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P. Srinivasa Rao
Lecturer
Electronics & Communication Engg.
Andhra Polytechnic, Kakinada
III semester
Digital Electronics
CM-305
Counters & Registers
50mts
UP/DOWN counter
PPT Diagrams
CM305.53

OBJECTIVES
On completion of this period, you would be able
to

Draw the circuit diagram of Up-down counter.

Know the principle of operation of the Up-down counter.

Draw the timing diagram of Up-down counter.

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Recollection
1. What is up counter?
It is the counter which is capable of progressing in the
forward direction, through a certain counting sequence.
Ex: A 2-bit binary counter with a upward counting
sequence of 0,1,2,3.
2. What is down counter?
It is the counter which is capable of progressing in the
reverse direction, through a certain counting sequence.
Ex: A 2-bit binary counter with a downward counting
sequence of 3,2,1,0.
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. What is meant by Edge triggering?

It means that the flip flop is changing the state either
at the positive edge (raising edge) or at the negative
edge (falling edge) of the clock pulse.

4.

Draw the clock pulse showing positive & negative

edge triggered type.
Rising
edge

Falling edge

CM305.53

CM305.53

UP/DOWN SEQUENCE FOR A

COUNTER
Clock
pulse
0
1
2
3
4
5
6
7

UP

3-BIT BINARY

QC

QB

QA

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

CM305.53

DOWN

Principle of 3-bit UP/DOWN counter

UP/DOWN is a control input which determines the
basic operation of the counter.
When UP/DOWN input is at high UP mode of operation is to
be performed .
When UP/DOWN input is at low DOWN mode of operation is
to be performed.
The out put of the counter is given by Q= QC QB QA
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 In this counter flip flop in the lower order position is

complemented with every clock pulse .
From the truth table notice that QA changes for every
clock pulse for both UP/DOWN sequences.

First flip flop toggles on each clock pulse because of J

&K inputs are at HIGH .

CM305.53

UP MODE OF OPERATION

When QA=1, QB changes its state on the next clock

pulse.
When the first clock pulse occurs, QA=1&QB = 0.
At the second clock pulse QA=0 & QB=1.

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 The output of Qc changes its state on the next

clock pulse when QA=QB=1.

When the fourth clock pulse occurs Qc changes its

state from 0 to 1.

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CONDITIONS FOR UP MODE OF OPERATION:

Control input UP/ DOWN must be at HIGH.
J&K inputs of second flip flop must be equal to 1 under the
condition
JB=KB=QA.UP.
Similarly the inputs of the third flip flop must be equal to 1
under the condition

JC=KC=QA.QB.UP.

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11

DOWN MODE OF OPERATION:

The output QB changes its state on the next clock pulse

when QA=0.
Qc changes its state on the next clock pulse when
QA=QB=0.

The above two changes can be observed from the truth

table.
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CONDITIONS FOR DOWN MODE OF OPERATION

UP / DOWN input must be at low.

J and K inputs of second flip flop must be equal to 1 under

the condition
JB=KB=QA.DOWN

J and K inputs of the third flip-flop must be equal to 1 under

the condition
JC=KC=QA.QB.DOWN
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TIMING DIAGRAM

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Note from the Timing diagram

Counter starts in the all 0s state and is positive edge

triggered.
Up operation is performed upto the trailing edge of the
forth clock pulse .

Down operation is performed from fourth clock pulse.

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SUMMARY
the circuit diagram of Up-down counter.
the principle of operation of the Up-down counter.
the timing diagram of Up-down counter.

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QUIZ
1.

The counter which is capable of progressing in the

forward direction is called

a) up counter
b) Down counter
c) decade counter
d) ripple counter

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2.

Preset and clear inputs are called

a)

synchronous inputs

b)

asynchronous inputs

c) control inputs
d) timing inputs

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3. In the case of up operation Up / Down pin becomes

a) 0
b) 1
c) High
d) both b & c

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4. In Mod-16 up counter the no. of flip-flops are

a) 1
b) 2
c) 3
d) 4

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Questions
1.

Draw the logic circuit of up/ down counter

2.

Explain the working of up/down counter

3.

Is the up/ down counter can be classified as

synchronous counter of asynchronous counter?

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