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Outline
Aim of the Project
Introduction
Objective
Literature survey
Design Methodology
Conclusion
References
INTRODUCTION
In domain of digital signal processing, logarithmic
OBJECTIVE
look-up table based algorithms: faster and
LITERATURE SURVEY
H. Hassler and N. Takagi, Function evaluation by
Contd..
Tso-Bing Juang, Shen-Fu Hsiao and Ming-Yu Tsai, "Para-
Contd..
D.R.LLAMCCA-OBREGON, C.P.AGURTO-RIOS, Fixed
serial is proposed.
Contd..
Shaowei Wang, Yuanyuan Shang, Hui Ding, Chen Wang and Junming Hu,
This study introduces the basic principles of the mode of calculation of the
hyperbolic systems by using the CORDIC algorithm, then analyses the FieldProgrammable Gate Array (FPGA) CORDIC core processing unit in detail. The
biggest advantage of the CORDIC algorithm is that its circuit structure is very
simple, using only adder and shifter. It is very suitable for FPGA implementation.
Based on the iterative algorithm, a FPGA implementation of the natural logarithmic
function has been designed. The pipelined-FPGA architecture can achieve a high
computational speed, for completing a computation only requires one clock cycle. The
relative error values are below 10-4, which can satisfy the accuracy requirements.
Contd..
Volder, J.E., 1959. The CORDIC trigonometric computing
Contd..
R. Ranga Teja, P. Sudhakara Reddy, IEEE, Member.
Design Methodology
CORDIC IP core of Xilinx ISE software, plus the
ln r
2
Data Initialization
fixed-point 2s complement numbers with an integer
CORDIC Algorithm
The CORDIC algorithm involves rotation of a vector '
Contd..
where ( xin ,yin) and (xout , yout) are the initial and
Contd..
Natural logarithm values can be got by doubling
inputs.
This part provides a base change by multiplying a
Contd..
CORDIC Architecture
Contd..
Types of CORDIC Architecture
1. Sequential Architecture
2. Parallel Architecture
3. Pipelined Architecture
Contd..
Pipelined CORDIC Algorithm
The ideal architecture depends
point position.
Data input is of 48 bit format. Of which first bit sign
bit and 1 bit integer and remaining fractional bit.
Work Completed
Implementation of Data Initialization in VHDL.
Remaining Work
CORDIC Pipelined IP Core.
Conclusion
In this project, we have introduced N logarithmic values for the
References
[1] H. Hassler and N. Takagi, Function evaluation by
Contd..
[4] I. Koren, "Computer arithmetic algorithms, 2nd
Contd..
Shaowei Wang, Yuanyuan Shang, Hui Ding, Chen Wang and
Thank You