Lab 3

Jorge Crichigno
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Half-adder

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Half-adder Testbench

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Waveform for half-adder simulation tb

stimulus
0

10 ns
testbench
ha

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x_signal

y_signal

s
c

s_signal
c_signal

Full-adder

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Full-adder Testbench

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Waveform for full-adder simulation tb

testbench
fa
x_signal

y_signal

z_signal
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s
c

s_signal
c_signal

Lab 3 - Sequential Statements

Process. Type of processes. Process with sensitivity list. Process
with wait statement. Example.
Sequential Signal Assignment Statement. Syntax. Examples.
Pitfall. Intermediate value. Conceptual implementation

Variables. Syntax. Intermediate value. Example. Conceptual

implementation
Case statement. Syntax. Example. Multiplexor. Conceptual
implementation.

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Lab 3 - Sequential Statements

Process
Contains a set of sequential statements to be executed sequentially
The whole process is a concurrent statement
Can be interpreted as a circuit part enclosed inside of a black box

Two types: with sensitive list and with wait statement

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Lab 3 - Sequential Statements

A process with a sensitivity list
Syntax
process (sensitivity_list)
declarations;
begin
sequential statement;
sequential statement;
...
end process;

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Lab 3 - Sequential Statements

Process with sensitivity list.
Interpretation: black box, indivisible circuit part.

Sensitivity list

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Note:

The execution of the process is initiated

whenever an event occurs on any of the signals
in the sensitivity list
For practical purposes, you can regards a
process as a big concurrent signal
assignment statement

Waveform for Example 1

Process not
activated on B
change

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0
0

1
1

00
00
00

00
11
00

A Process With wait Statement

Process has no sensitivity list

Process continues the execution until a wait statement is reached and
then suspended
Forms of wait statement:
wait on signals;
wait until boolean_expression;
wait for time_expression;

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Sequential Signal Assignment Statement

Syntax: Signal_name <= value_expression;

S1
C

undefined

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0
0

0
1

1
0

1
1

1
U

0
U

1
U

Sequential Signal Assignment Statement

If all assignments are within DELTA-delay, only the last
assignment takes effect. You can think as the signals are not
updated until the end of the process (i.e., it never assumes any
intermediate value).

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Variable Assignment Statement

Syntax: Variable_name := value_expression;
Used inside processes. The assignment takes effect immediately.

Note:
Easy to understand, but not clear hardware
mapping!
Use signal always you can; rely on variables
only for the characteristics that cannot be
described by signals

0
A

Conceptual
implementation

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tmp

B
C

Case Statement
Syntax:

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Example:

Example of case statement: Multiplexor

Introduction to Multiplexers
Truth Table

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I0

I1

4-to-1 multiplexer VHDL Implementation

Architecture
Entity

ARCHITECTURE multiplexor4x1 OF mux4x1 IS

BEGIN

ENTITY mux4x1 IS

PROCESS(S, D0, D1, D2, D3)

PORT (

BEGIN

S : IN STD_LOGIC_VECTOR (1 downto 0);

CASE S IS

D0 : IN STD_LOGIC;

WHEN "00" =>

Y <= D0;

D1 : IN STD_LOGIC;

WHEN "01" =>

Y <= D1;

D2 : IN STD_LOGIC;

WHEN "10 =>

Y <= D2;

D3 : IN STD_LOGIC;

WHEN OTHERS => Y <= D3;

Y : OUT STD_LOGIC
);
END mux4x1;

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END CASE;
END PROCESS;
END multiplexor4x1;