Chapter 5

Flip-Flops, Registers,
and Counters


Chapter 4
Combinational Circuits
Commonly used combinational circuits
Multiplexers, which can be used for
selection of signals
Circuits used for encoding, decoding and
code-conversion purposes
Verilog constructs used to define
combinational circuits
Chapter 5 Flip-Flops, Registers,
and Counters
Logic circuits that can store information
Flip-flops, which can store a single bit
Registers, which store multiple bits
Shift registers, which shift the contents of
the register
Counters of various types
Verilog constructs used to implement
storage elements
Sequential Circuits
Combinational circuits value of each
output depends solely on the values of input
Another class of logic circuits values of
the outputs depend NOT only on the present
values of inputs but also on the past
behavior of the circuits
Such circuits include storage elements that
store the value of logic signals
Contents of the storage element represent
the state of the circuits
Figure 5.1. Control of an alarm system.
Memory
element
Alarm
Sensor
Reset
Set
On Off
Motivation
Figure 5.2. A simple memory element.
A B
Motivation
The circuit will maintain these values
indefinitely because of the feedback loop
Set Latch
Consider an OR gate.
(Assume both inputs are at logic 0)
If the output is connected back to one of the inputs, the
gate remains stable with an output of 0.
If logic 1 is applied to input S, the output of OR
becomes logic 1.
Even changing the input S back to 0, the output Q
remains at logic 1. So this device permanently set to
logic 1. Therefore this is called a set latch.
Reset Latch
Let us replace, OR gate with NOR and NOT
gates cascade.
Reset Latch
The output of NOR gate is now selected as the gate
output Q.
Applying logic 1 to input R will force the feed back
signal to 1, thus the latch output Q is reset to logic 0.
Even R is returned to logic 0, because of the feedback
signal, the latch output Q will remain at logic 0
permanently. Therefore this is called a reset latch.
S latch redrawn with a NOR and NOT gates.
Reset Latch
Another view of previous reset latch circuit.
Set-Reset Latch
However, devices that stay permanently in
one logic state are not very useful
If we combine the features of both latches
into one circuit, we can set or reset the latch
as needed.
Basic Latch
Feedback connection of two NOR gates or
two NAND gates, which can store one bit of
information
It can be set to 1 using the S input and reset
to 0 using the R input
Figure 5.3. A memory element with NOR gates.
Reset
Set Q
Basic Latch
Figure 5.4. A basic latch built with NOR gates.
S R Q
a
Q
b
0 0
0 1
1 0
1 1
0/1 1/0
0 1
1 0
0 0
(a) Circuit (b) Truth table
Time
1
0
1
0
1
0
1
0
R
S
Q
a
Q
b
Q
a
Q
b
?
?
(c) Timing diagram
R
S
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
(no change)
Limitations of Basic Latch
Timing is unknown - asynchronous
Output oscillation
Control strategy - reset equal to 1
Gated Latch
Basic latch that includes input gating and a
control input signal
Retains its existing state when the control
input is equal to 0
Control input as the clock
Two types of gated latch:
Gated SR Latch
Gated D Latch
Gated SR Latch
S set the latch, to 1
R reset the latch, to 0
Figure 5.5. Gated SR latch.
Figure 5.6. Gated SR latch with NAND gates.
S
R
Clk
Q
Q
Construct latch using NAND gates
Clock is gated by NAND gates
S and R inputs are reversed
Limitations of Gated SR Latch
Output oscillation
Gated D Latch
Uses the D input to force the latch into a
state that has the same logic value as the D
input
Single data input, D
It stores the value on this input, under the
control of a clock signal
Figure 5.7. Gated D latch.
Limitations of Gated D Latch
Output signal changes while clk = 1