ARITHMETIC

LOGIC UNIT (ALU)

The ALU is the part of the computer that actually
performs arithmetic and logical operations on
data. All of the other elements of the computer
system-control unit, registers, memory, I/O are
there mainly to bring data into the ALU for it to
process and then to take the results back out.
An ALU and, indeed, all electronic components in
the computer are based on the use of simple
digital logic devices that can store binary digits
and perform simple Boolean logic operations.
OBE TECHNIQUE: GALLERY WALK
Representation of integers - sign-magnitude,
ones complement, twos complement.
Sign magnitude rep. - rep., drawbacks
2s complement rep.- characteristics,
examples, geometric depiction,adv.,special
cases, use of value-box for conversion, sign
extension
Arithmetic with 2s complement numbers-
Addition/Subtraction/Multiplication/Division
Computer do not store numbers or letters

Computers store bit sequences

The bit sequences can be interpreted as
representing integers or floating point numbers

Arithmetic is accomplished by the direct
hardware implementation of the arithmetic
algorithms.

Does the calculations
Everything else in the computer is there to
service this unit
Handles integers
May handle floating point (real) numbers
May be separate Floating Point Unit (maths
co-processor)

Only have 0 & 1 to represent everything
8 bits word could be used to represent the non-negative
numbers from 0 to 255.
Positive numbers stored in binary
e.g. 41=00101001
No minus sign and No period (radix point) for computer
storage and processing
General - n-bit sequence: a
n-1
a
n-2
..a
1
a
0
is interpreted as
unsigned integer A, then

n-1

A = 2
i
a
i


i=0

Representation of negative integers - Sign-Magnitude, ones
complement, Twos complement, Biased

Left most bit is sign bit
0 means positive
1 means negative
+24 = 00011000
-24 = 10011000
n-2

A = 2
i
a
i ,
if a
n-1
=0

i=0

General case A =
n-2

A = - 2
i
a
i ,
if a
n-1
= 1

i=0
The rule for forming the negation of an integer is
invert the sign bit.

For taking n-bit integer and store in m bits,
m>n
For sign- magnitude, move the sign bit to
the new left-most position and fill in with
zeros.
+18 = 0001 0010 (sign
magnitude,8bits)
+18=0000 0000 0001 0010 (16 bits)
-18= 1001 0010 (8 bits)
-18=1000 0000 0001 0010 (16 bits)

Adders: Logical gates to add two numbers
We need to use a circuit
with more than one
output, which clearly
more powerful than a
Boolean expression.



Consider adding two 1-bit binary numbers x
and y
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10

Carry is x AND y
Sum is x XOR y
The circuit to compute this is called a half-
adder
x y Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Half adder implemented
using XOR and AND gates
x y s c
1 1 0 1
1 0 1 0
0 1 1 0
0 0 0 0
Half adder implemented using OR, AND and
NOT gates
HA
X
Y
S
C
HA
X
Y
S
C
x
y
c
c
s
x 1 1 1 1 0 0 0 0
y 1 1 0 0 1 1 0 0
c 1 0 1 0 1 0 1 0
s (sum) 1 0 0 1 0 1 1 0
c (carry) 1 1 1 0 1 0 0 0
The full circuitry of the full adder
14
x
y
s
c
c
Just chain one half adder and full adders together,
e.g., to add x=x
3
x
2
x
1
x
0
and y=y
3
y
2
y
1
y
0
we need:
15
HA
X
Y
S
C
FA
C
Y
X
S
C
FA
C
Y
X
S
C
FA
C
Y
X
S
C
x
1
y
1
x
2
y
2
x
3
y
3
x
0
y
0
s
0
s
1
s
2
s
3
c
A half adder has 4 logic gates
A full adder has two half adders plus a OR gate
Total of 9 logic gates
To add n bit binary numbers, you need 1 HA and
n-1 FAs
To add 32 bit binary numbers, you need 1 HA and
31 FAs
Total of 4+9*31 = 283 logic gates
To add 64 bit binary numbers, you need 1 HA and
63 FAs
Total of 4+9*63 = 571 logic gates
16
An n-bit adder may be constructed by
cascading n 1-bit address. Sum will be
delayed with respect to CARRY. In the case of
an n-bit parallel adder, the carry delay.
Parallel adders are digital circuits that
compute the addition of variable binary
strings of equivalent or different size in
parallel.

Parallel Adder block diagram
http://www.play-
hookey.com/digital/binary_subtraction
.html
Introduction
Shift registers are a type of sequential logic
circuit, mainly for storage of digital data. They
are a group of flip-flops connected in a chain
so that the output from one flip-flop becomes
the input of the next flip-flop.
Most of the registers possess no characteristic
internal sequence of states. All flip-flop is
driven by a common clock, and all are set or
reset simultaneously.
Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike combinational logic is
not only affected by the present inputs, but also, by the prior history. In other words, sequential logic
remembers past events.
Shift registers produce a discrete delay of a digital signal or waveform. A waveform synchronized to a
clock, a repeating square wave, is delayed by "n" discrete clock times, where "n" is the number of shift
register stages. Thus, a four stage shift register delays "data in" by four clocks to "data out". The stages
in a shift register are delay stages, typically type "D" Flip-Flops or type "JK" Flip-flops.
Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert parallel
data to serial form. Serial data communications replaces many slow parallel data wires with a single
serial high speed circuit.
Serial data over shorter distances of tens of centimeters, uses shift registers to get data into and out of
microprocessors. Numerous peripherals, including analog to digital converters, digital to analog
converters, display drivers, and memory, use shift registers to reduce the amount of wiring in circuit
boards.
Some specialized counter circuits actually use shift registers to generate repeating waveforms. Longer
shift registers, with the help of feedback generate patterns so long that they look like random noise,
pseudo-noise.
Basic shift registers are classified by structure according to the following types:
Serial-in/serial-out
Parallel-in/serial-out
Serial-in/parallel-out
Universal parallel-in/parallel-out
Ring counter

Serial-in, serial-out shift registers delay
data by one clock time for each stage.
They will store a bit of data for each
register. A serial-in, serial-out shift register
may be one to 64 bits in length, longer if
registers or packages are cascaded.
Serial in/serial Out shift register using type
D flip-flop
A serial-in/parallel-out shift register is
similar to the serial-in/ serial-out shift
register in that it shifts data into internal
storage elements and shifts data out at the
serial-out, data-out, pin. It is different in that
it makes all the internal stages available as
outputs. Therefore, a serial-in/parallel-out
shift register converts data from serial
format to parallel format. If four data bits
are shifted in by four clock pulses via a
single wire at data-in, below, the data
becomes available simultaneously on the
four Outputs Q
A
to Q
D
after the fourth clock
pulse.



The purpose of the parallel-in/
parallel-out shift register is to take in
parallel data, shift it, then output it as
shown below. A universal shift register
is a do-everything device in addition to
the parallel-in/ parallel-out function.


The 74HC195 can be used for parallel in/parallel
out operation, serial in/serial out and serial
in/parallel out operations. Q3 is the output
when it is used for parallel in/serial out
operation.

FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS195A 4-Bit Shift
Register. The device is useful in a wide variety of
shifting, counting and storage applications. It performs
serial, parallel, serial to parallel, or parallel to serial
data transfers at very high speeds.

The LS195A has two primary modes of operation, shift
right (Q0 " Q1) and parallel load which are controlled by
the state of the Parallel Enable (PE) input. When the PE
input is HIGH, serial data enters the first flip-flop Q0
via the J and K inputs and is shifted one bit in the
direction Q0 " Q1 " Q2 "Q3 following each LOW to HIGH
clock transition. The JK inputs provide the flexibility of
the JK type input for special applications, and the
simple D type input for general applications by tying
the two pins together.
When the PE input is LOW, the LS195A appears
as four common clocked D flip-flops. The data on the parallel
inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,
Q2, Q3 outputs following the LOW to HIGH clock transition.
Shift left operations (Q3 "Q2) can be achieved by tying the Qn
Outputs to the Pn1 inputs and holding the PE input LOW.

All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since the
LS195A utilizes edge-triggering, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operation
except for the set-up and release time requirements.
A LOW on the asynchronous Master Reset (MR) input sets
all Q outputs LOW, independent of any other input condition.
THREE logical operations in ALU : AND, OR and
NOT. The truth table of the three logics operation
respectively shown below.

Multiplexer(Mux)
A combinational circuit that receives binary information from one of 2
n
input data
lines and directs it to a single output line
A 2
n
-to 1 multiplexer has 2
n
input data lines and
n input selection lines(Data Selector)
4-to-1 multiplexer Diagram : Fig. 2-4
4-to-1 multiplexer Function Table : Tab. 2-3



Quadruple 2-to-1 Multiplexer
Quadruple 2-to-1 Multiplexer : Fig. 2-5

Select Output
S1 S0 Y
0 0 I
0
0 1 I
1
1 0 I
2
1 1 I
3
I
0

I
1

I
2

I
3


S0
S1
Y
Tab. 2-3 Function Table for
4-to-1 line Multiplexter
Fig. 2-4 4-to-1 Line Multiplexer
Select Output
E S Y
0 0 All 0's
1 0 A
1 1 B
Quadrup
le
2 x 1
Mux
A
0
A
1

A
2

A
3

B
0
B
1

B
2

B
3


Y
0
Y
1

Y
2

Y
3


Enable
Select
Fig. 2-5 Quadruple 2-to-1
line Multiplexter
(a) Function Table (b) Block Diagram

You can make even larger multiplexers, following the same pattern.
A 2n-to-1 multiplexer routes one of 2n input lines to the output line.
There are 2n data inputs, so there must also be n select inputs.
The output is a single bit.
Here is an 8-to-1 multiplexer, probably the biggest well see in this
class.
Two multiplexers in single IC at gate level