1

Charge Pump PLL

2
Outline
Charge Pump PLL
Loop Component Modeling
Loop Filter and Transfer Function
Loop Filter Design
Loop Calibration
3
Charge Pump PLL
The charge pump PLL is one of the most
popular PLL structures since 1980s
Featured with a digital phase detector and a
charge pump
Advantages
Fast lock and tracking
No false lock

Phase
Detector
Charge
Pump
Loop
Filter
VCO
N-Divider
f
i
f
o
f
o
4
Phase Detector
Gives the phase difference between the input
clock signal and VCO output signal
Different types
Nonlinear (such as Bang-Bang)
Linear (such as Hogges Phase Detector)
Linear PD output a digital signal whose duty
ratio is proportional to the phase difference
In Hogges PD, if the phase difference is
e
, the
output digital signal duty ratio is

2
e
C. Hogge, A Self-correcting clock recovery circuit, Dec, 1985
5
Typical Phase Detector and Waveform
Y. Tang, et., al., "Phase detector for PLL-based high-speed data recovery," Nov. 2002
Circuit
Structure
Output
Waveform
When locked
2
1
6
Charge Pump
Convert a digital signal into current
UP
DN
I
up
I
dn
P
I
7
Loop Filter
Low pass filter
1
st
order
2
nd
order (higher roll-off speed at high
frequency)
3
rd
order & higher
) (
1
) (
2 1 2 1
2
1
C C s C RC s
sRC
s F

I
p
V
C
C1
R
I
p
V
C
C1
R
C2
1
1
) (
sC
R s F
8
VCO
Tuning gain K
VCO
is the most important
parameter
Usually coarse tuning and fine tuning

s
K
VCO
9
CP PLL loop modeling
Phase
Detector
Charge
Pump
Loop
Filter
VCO
f
i
f
o
f
o
i
o
10
2
nd
Loop Transfer Function
Using a 1
st
order LPF: Active PI type
Open-loop transfer function


Closed-loop transfer function



1
2
2
1
1
) (
C s
) (sRC
VCO
K
p
I
s
o
G

1
2 2
2
1
2 2
C
VCO
K
p
I

R
VCO
K
p
I
s s
C
VCO
K
p
I

R
VCO
K
p
I
s
(s)
c
G

11
3
rd
Loop Transfer Function
Using a 2
nd
order LPF
Let m=C2/C1
Open-loop transfer function


Closed-loop transfer function



) 1 (
2
1
3
1
2 2
)
2 1
(
2
2 1
3
) 1
1
(
2
) (

m s mRC s
C
VCO
K
p
I R
VCO
K
p
I
s
C C s C RC s
sRC
VCO
K
p
I
s
o
G

1
2 2
) 1 (
2
1
3
1
2 2
) (
C
VCO
K
p
I R
VCO
K
p
I
s m s mRC s
C
VCO
K
p
I R
VCO
K
p
I
s
s
c
G

12
Comparison
When m becomes 0, the 3
rd
order loop
degenerates into 2
nd
order loop
3
rd
order loop gives an extra high frequency
pole, which increases the high frequency roll-off
in jitter transfer
3
rd
order loop is widely used and can be treated
as 2
nd
order loop for simplification
Unfortunately, the 3
rd
order loop shows different
jitter transfer from the 2
nd
order loop
We focus on 3
rd
order loop
13
Simplification of 3
rd
Order Loop
Define natural frequency
n
& damping ratio



Then totally 3 loop parameters:
n
, &m
Simplified transfer function
1
2
2
C
VCO
K
p
I
n

2
2
VCO p
n
RK I

2 2 3
2
2 ) 1 (
2
2
) (
n n
n
n n
c
s s m s m
s
s G

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LPF Design Consideration
3-dB frequency easy to control
Roll-off speed easy to meet with 2
nd
and 3
rd

order transfer function
Jitter transfer (jitter peaking)
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Jitter peaking of 2
nd
order loop
Jitter peaking can be reduced or
eliminated by increasing the damping ratio
Eliminated when damping ratio >1
Large damping ratio leads to slow closed-
loop response
Usually suggested =5 to meet the jitter
peaking spec
16
Jitter peaking of 3
rd
order loop
Usually believed to be similar as the 2
nd

order loop
Actually quite different from the 2
nd
order
loop case
Jitter peaking always exists even with very
large
Need to be treated carefully
17
Jitter peaking is dependent on and m

m=0 (2nd loop)
jitter peaking can be
reduced or eliminated by using
large
m>0 (3rd loop)
is quite small, increasing
will decrease the jitter
peaking;
is larger than a threshold
value
m
, increasing will
increase the jitter peaking
Jitter peaking versus damping ratio and capacitance ratio
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How to achieve the minimum jitter peaking

For given m, there exists the
minimum jitter peaking
--the minimum jitter peaking
can be viewed as a function of
m: JP(m)
The minimum jitter peaking
under a given m is achieved
only by using a proper
-- should be a function of m:

m
(m)
JP(m)
m(m)

19
Sampling effect of phase detector
The phase detector has sampling effect,
especially when its rate is not much higher
than the loop cut-off frequency
Approximate TF of phase detector :

2
1 e - 1
) (
P
-sT

P
PD
sT
s H
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Jitter Peaking w/ PD Sampling Effect
It causes the jitter
peaking worse
when is very small, jitter
peaking decreases when
increases;
when becomes larger
than
m
, jitter peaking
increases with ;
when is larger than
m2
,
jitter peaking decreases
when is increased further

21
JP(m) and
m
(m) with sampling effect
JP(m) with sampling effect
m
(m) with sampling effect
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Tables of JP(m) and
m
(m) for
practical design
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Design procedures of charge pump PLLs
for jitter transfer characteristic optimization

1. Decide the maximum tolerated jitter peaking and find
capacitance ratio m using JP(m).
2. Use
m
(m) to find the optimal damping ratio value m;
3. Decide
n
according to the application, choose
reasonable K
VCO
, and calculate I
p
, R, C
1
and C
2
;
4. Use time domain simulation to verify that the expected
jitter transfer performance can be achieved
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Design example

Target: to design a
2.5GHz CP PLL, meet
the jitter specification
Design parameters:
m=0.005 and =5.0
Simulation result: jitter
peaking is only 0.078dB

Jitter transfer characteristic of the designed PLL
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More Discussion on Loop Transfer Function
The above discussion suggests to use
very small m to meet the jitter peaking
However, if m is too small, the effect of the
second capacitor can even be ignored
Compromise should be made between
jitter peaking and other performance
26
Charge pump PLL calibration
Purpose: make the loop transfer
characteristic meet the spec
Calibration types:
Component calibration
Loop calibration
27
Charge Pump Calibration
Purpose: minimize the mismatching
between UP and DOWN current
Method: switch small current sources
UP
DN
I
up
I
dn
UP
DN
I
up
I
dn

I
CAL
I
CAL I
CAL
I
CAL
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Charge Pump Calibration
Procedure
Use the UP or Down current to
charge/discharge a capacitor
Compare the time difference and calculate
the calibration code
UP
DN
I
up
I
dn
Vref
Comparator
Counter
Ref CLK
R/S
29
VCO Coarse Tuning
Purpose: to speed frequency tracking
Method: make use of the coarse tuning
functionality of the VCO
When extreme high frequency range is
desired, double VCOs can be used to help
achieve fine frequency tuning resolution
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VCO Coarse Tuning Procedure
Apply different coarse tuning voltage
(output from a low resolution coarse tuning
DAC)
Measure VCO output frequency
respectively
Compare to the reference frequency
Write the desired DAC code into register
31
Time Constant Calibration
Purpose: calibrate the loop transfer
function time constant so that the 3-dB
frequency meets the spec
Method: switch small CAL capacitors

C
CAL
C
CAL C
CAL
C
CAL
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Time Constant Calibration Procedure
t
RC
Vref
t V
X
) (
Vref
Comparator
Counter
Ref CLK
R
Vref
R
C
Vx
RC f Counter
ref
#
33
Loop Gain Calibration
Purpose: calibrate the loop transfer gain to
the desired value
Method: switch different charge pump
output current (K
VCO
is not changeable
usually)