Chapter 9: Synchronization

Shanghai Jiao Tong University

2011.11
Synchronization
Synchronization is one of the most critical functions performed at the
receiver of a synchronous communication system. To some extent, it is the
basis of a synchronous communication system.
Carrier synchronization
Symbol/Bit synchronization
Frame synchronization
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Synchronization
Carrier synchronization
To recover the signal without distortion, receiver needs
to estimate and compensate for frequency and phase
differences between a received signals carrier wave and the
receivers local oscillator for the purpose of coherent
demodulation.
As to digital communication system, symbol/bit
synchronization and frame synchronization are also
required.
2011.11
Frame synchronization
Receiver can proceed by every group of symbols instead of every
single symbol, such as a frame in TDM system. Similar with symbol/bit
synchronization, the process of extracting such a clock signal is called
frame synchronization.
Symbol/bit synchronization
The output of the receiving filter must be sampled at the symbol
rate and at the precise sampling time instants. Hence, we require a clock
signal. The process of extracting such a clock signal at the receiver is
called symbol/bit synchronization.
Synchronization
Synchronization
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The synchronized system required:

Synchronous signal must have high noise immunity and be reliable.
Generating synchronous signal should not consume much extra power and
increase implementation complexity.
Synchronous signal should possess few channel resource.
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PLL is a feedback loop with a voltage-controlled oscillator (VCO), a phase
detector (PD)and a loop filter (LF). The PD will generate the phase difference
of v
i
(t) and v
o
(t). The VCO will adjust the oscillator frequency based on this
phase difference to eliminate the phase difference. At steady state, the output
frequency will be exactly the same with the input frequency.
Phase-locked Loop
2011.11
Phase-locked Loop
)] ( cos[ ) (
)] ( sin[ ) (
0
0
t t v t v
t t v t v
o o
i i
.
+ =
+ =
| e
| e
) ( sin K )] ( ) ( sin[ K ) ( t t t t v
e d d d
| | | = =
.
Loop filter is also a LPF. Active/passive PI filter are most commonly used.
A PD contains a multiplexer and a lowpass filter. The LPF is for filtering
the extra frequency component generated by multiplexing. The output voltage
is:
) ( ) ( ) ( t v p F t v
d c
=
dt
d
p =
The output of the LF is:

2011.11
Phase-locked Loop
) ( K
) (
t v
dt
t d
c v
=
.
|
The output of VCO can be a sinusoid or a periodic impulse train. The
differentiation of the output frequency are largely proportional to the input
voltage.
If F(p)=1Then
) ( sin K
) (
t
dt
t d
e
|
|
=
.
This kind of loop is called the first-order loop
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Phase-locked Loop
In a coherence system, a PLL is used for:
1. PLL can track the input frequency and generate the output signal with
small phase difference.
2. PLL has the character of narrowband filtering which can eliminate the
noise introduced by modulation and reduce the additive noise.
3. Memory PLL can sustain the coherence state for enough time.

CMOS-based integrated PLL has several advantages such as ease of
modification, reliable and low power consumption, therefore are widely
used in coherence system.
2011.11
Carrier Synchronization
To extract the carrier

1. Pilot-tone insertion method
Sending a carrier component at specific spectral-line along with the signal
component. Since the inserted carrier component has high frequency stability,
it is called pilot.

2. Direct extraction method
Directly extract the synchronization information from the received
signal component.
2011.11
Pilot-tone insertion method
Modulator
Bandpa
ss
filter
Add
s(t)
x(t)
t/2phase
shift
-asin(e
c
t)
cos(e
c
t)
1. Pilot-tone insertion method
insert pilot to the modulated signal
( ) ( )
cos sin
c c
s t f t t a t e e =
Thinking
Why 90
0
shift

The pilot signal is generated by shift the carrier by 90
0
and decrease by several
dB, then add to the modulated signal. Assume the modulated signal has 0 DC
component, then the pilot is
2011.11
X(f)
f
x
0 f
S(f)
0
f
c

f
c
-f
x
f
c
+f
x

Pilot-tone insertion method
The receiver uses a narrowband filter with central frequency f
c
to extract the
pilot and then the carrier can be generated by simply
shifting 90
0
.
sin
c
a t e
cos
c
a t e
2011.11
( ) ( ) ( )
( ) ( )
( ) ( )
2
1
0
cos cos sin cos
1 1 1
cos 2 sin2
2 2 2
1
s
2
c c c c
c c
s t s t t f t t a t t
f t f t t a t
After the LPF t f t
e e e e
e e
= =
= +
=
Pilot-tone insertion method
DSB, SSB and PSK are all capable of pilot-tone insertion method. VSB can
also apply pilot-tone insertion method but it is more complex.
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Narrowband Filter
The drawback of narrowband filter:
The pass band is not narrow enough
f
c
is fixed, do not tolerate any frequency drift with respect to the central
frequency

Can be replaced by PLL




Pilot-tone insertion method is suitable for DSB, SSB, VS and 2PSK
2011.11
Direct extraction method
2. Direct extraction method


1).If the spectrum of the received signal already contains carrier
component, then the carrier component can be extracted simply by a
narrowband filter or a PLL.
2).If the modulated signal already eliminates the carrier component, then
the carrier component can be extracted by performing nonlinear
transformation or using a PLL with specific design.
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Nonlinear-transformation-based method
1. Square transformation
( ) ( )
( ) ( )
( ) ( ) ( )
( ) ( ) ( )
( )
2 2 2
2 2
2
Example a DSB signal cos
1 1
s cos 2
2 2
1 1
2
c
c
m
s t f t t
If f t s t does not have carrier component
t f t f t t
now f t f t f t
then s t
e
e
o o
o
=
= +
= +
= +

has 0 DC componentthen
square transformation:
contains DC component,let it be so
( )
1 1
cos 2 ( ) cos 2
2 2 2
m c m c
f t t f t t o e e + +
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Nonlinear-transformation-based method
( ) ( ) t t f t t f t s
c m c m
e e o o 2 cos ) (
2
1
2 cos
2
1
2
1
2
1
2
+ + + =
2
2
c
c
e
e
The first term is the DC component. The second term is the low
frequency component. The third term is the component. The
4th term is the frequency component symmetrical distributed of
modulation noise. After narrowband filtering, only the 3rd
term and a small fraction of 4th term left, then the carrier
component can be extracted by frequency division.
Since the carrier is extracted by freq
o
uency division, its phase
may shift by 180 . Besides, modulation noise may cause random
phase jitter.
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Nonlinear-transformation-based method
Square PLL
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In-phase orthogonal loopCostas Loop
2. In-phase orthogonal loop Costas Loop
Contains in-phase branch and orthogonal branch. All parts
except LF and VCO are similar with a phase detector.
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( ) ( )
( ) ( ) ( ) ( ) ( )
( ) ( )
( ) ( )
1
1
Let s cos
1
1 1
cos sin sin sin 2
2 2
1
After LPF sin
2
1
2
(
c
c c e e c e
e
e
e e
t f t t
f t t t f t f t t
r t f t
When r t f t
e
e e | | e |
|
|
| |
=
+ = + +
=
=
upper branch
is the phase difference between generated carrier and the original carrier
is small
( ) ( ) ( )
( ) ( ) ( )
2
2
2
2)
1 1
cos
2 2
1
(3) ( )
4
e
1 e d
r t f t f t
r t r t f t v t
|
|
=
=
lower branch
In-phase orthogonal loopCostas Loop
2011.11
In-phase orthogonal loopCostas Loop
( ) ( )
c
2
1.Costas loop works on instead of 2 so when f is large
Costas loop is easier to realize
2.The output of in-phase loop r is the signal f
c c
f f
t t
Advantages of Costas loop

2011.11
Performance
3. Performance of carrier synchronization technique


1) Phase error: steady-state phase error, random phase error
2) Synchronization build time and hold time
2011.11
Performance
0
c
1. steady-state phase error
(1) Narrowband filter is a simple single tuned loop with a fixed
Q value. When the central frequency is not equal to the carrier
frequency , steady-state phase error
e
|
| A
0
0
0
0
0
is arose.
Let
When is small
2 Q
(2) hen PLL is applied:
is the DC gain of the PLL circuit. Apparently, can have a
very small value as long as is large enough.
c
e
Q
W
k
k
k
e e e
e
| |
e
e
| |
|
A =
A
A = + A +
A
A = =
A


2011.11
2. Random phase error
Assume Gaussian random noise is the case, we already know when SNR is high
(SNR>>1), the phase distribution of the sum of a sinusoid signal and a gaussian noise
passed through a na
( )
( )
2
2
rrowband system is a gaussian distribution.
Let (0) 0, then:

1
with 0 we use to assess the random phase error.
2
1
random phase jitter
2
d
d
f e
f mean
d
d
|
| |
|

|
t
| o o
o

=
=
= =
=

Performance
2011.11
Performance
0
0 0
0 0
0 0
Example Narrowband filter is a single tuned loop.
The equivalent noise bandwidth:
2
Let the noise's single-sideband PSD is N then the noise power is
2

1
then
2
n
n n
S s
n
f
B
Q
P N B
P P Q
d
P N f
N f
d
|
t
t
t
o
=
=
= =
= =

4
Apparently Q , .
Based on above discussion, we can see there is a trade-off between minimize the
steady-state phase error and the random phase error.
S
QP
|
o | +
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3. Synchronization build time and hold time
Example: using single tuned loop to realize narrowband filtering
U
kU
ts
tc
t
Performance
2011.11
Performance
( ) ( )
( )
( )
0 0
0 0
0
0 0
(1) When t 0 the output voltage is:
1 cos
2 is the resonant frequency
When synchronization is build when the amplitude goes to 0 1
As: K 1
1 1
So ln syn
1
s
t
S
t
s
u t u e t
Q
t t Ku K
u u e
t
k
o
o
e
o e e
o

=
=
=
= < <
=
=

chronization build time

2011.11
Performance
( )
0
c 0
(2) When synchronization is build, cut off the input signal at 0, then the output is:
cos
When synchronization is hold until the amplitude decreases to
As KU U
1 1
ln
s
t
t
c
t
u t Ue t
t t Ku
e
So t
k
o
o
e
o

=
=
=
=
=

synchronization hold time

2011.11
Performance
In practice, we want , . However, when Q , , both and ,
vice versa. Therefore, we need consider both factors when designing the parameters.
When using PLL, t is the lock time, t is th
s c s c
s c
t t t t o + | | + |
e hold time. Their values depend on
the parameters of circuits. Similarly, there is also a conflict when picking parameters.
However, we can change the parameters after lock is build, therefore let t
s
+ and .
c
t |
1 1
ln
1
s
t
k o
=

1 1
ln
c
t
k o
=
0
2Q o e =
2011.11
Symbol Synchronization

In a digital communication system, the output of the receiving
filter must be sampled periodically at the symbol rate and at the
precise sampling time instance.
To perform this periodic sampling, we need a clock signal at the
receiver
The process of extracting such a clock signal is called symbol
synchronization or timing recovery
One method is for the transmitter to simultaneously transmit the
clock frequency along with the information signal. The receive can
simply employ a narrowband filter or PLL to extract it. This
method requires extra power and bandwidth and hence, but
frequently used in telephone transmission systems.
Another method is to extract the clock signal from the received
data signal by using some kind of non-linear transformation.
Early-Late Gate Synchronization
Basis Idea: exploit the symmetry properties of the output
signal of matched filter or correlator


2009.07 .
Due to the symmetry, the values of the
correlation function at the early
samples and the late
samples are equal.
Thus, the proper sampling time is the
midpoint between and
.
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Nonlinear-transformation-based method
1. Nonlinear-transformation-based method
Some transformations can add synchronous signal with f=1/T to the
original signal. For example, we can transform the signal to return-to-zero
waveform. After narrowband filtering and phase shifting, we can generate
the clock signal used for synchronization.
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Digital PLL (DPLL)
2. DPLL
2011.11
Digital PLL (DPLL)

2011.11
Performance
( ) rad n
e
t 2 =
3. Performance of symbol synchronization system
DPLL
1). Phase error
The phase error occurs because of for a DPLL, the phase cannot
change with arbitrary small value, each time the phase can only be
modified by 2/nn is the frequency division number. Therefore
the maximum of phase error is:
( ) s n T T
b e
=
In time domain, it is:
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2. Synchronization build time
Synchronization build time is the maximum period from the system lost synchronization
to the system back to synchronization state.
The maximum delay between the synchron
s
t
ous impulse and the received signal is 2
Each time the DPLL can only modify the phase by 2 so synchronization is build after
N times
2
2
The PDLL can only modify the phase when the receive
b
b
b
b
T
T n
T n
N
T n
= =
.

d code crosses zero point.

As to random binary code, we can approximately think '01' '10' '11' ' 00' appears with
same probability. Therefore, the code will cross zero point with probability 0.5. Thus
a


modification happens each 2 seconds.
Synchronization build time is
2
b
s b b
T
t T N nT = =

Performance
2011.11
3. Synchronization hold time
If the input signal is interrupted after synchronization is build, since there is a
frequency difference between the transmitter and the receiver, the phase of
c
t
F A the
synchronous signal will keep drifting. We consider the system is not synchronous
any more if the phase is drifted by a centain value. This period is called synchronization
hold time.
If the transm
1 2
1 2
2 1
1 2 2
1 2 1 2 0
0 1 2 0 0
0 1 2
0
1 2
0 0
1 1
itter and the receiver have T and separatively then
1 1

F and 1
It can also be written as

T
F F
F F F
T T
F F F F F
F F T F
F
F T T
F
T T F
T F
= =
A
= = =
= =
A
=
A
=

Performance
2011.11
1 2
0 0
When frequency difference exists the phase will drifted by after every
If the system can only allow the drift to be as large as ( is relevant with ),
then we can calculate the synchr
F T T
T T K K Pe
A
.
0
0
c
onization hold time as:

1
t
If fixed then the system requires to be:
1

If the oscillators in transmitter and receiver have the same
c
c
c
c
t
T k F
t F
F k
t F
F
t k
A
=
=
A
A
A =

0 0
stability, then the stability
should not below:
1

2 2
c
F
F t kF
A
=
Performance
2011.11
1 2 0
2
0 0
4. Synchronous bandwidth
ynchronous bandwidth is the range of .
The drift occurs during one symbol interval is
As mentioned, the DPLL modifies the phase every 2 symbol
s
f
S F
F F
T T T T
F F
A
A
A A
A = = =

0
0
2
0 0 0
0
0
s. Each time spends
seconds. To mentain synchronazation, obviously we need:
1 1

2 2 2
2
when F we have:
2
s
b
b s
T n
T F
T
n nF F nF
F
f F
n
f
f f
n
A
A s = s
A = A s
A s ,
Performance
2011.11
Performance
In DPLL, frequency division number n will affect and so n must be selected
properly to let satisfies the system's requirement and let ,
e s
e s c s
f
t t f
|
|
A
+ | A |

2011.11
Frame Synchronization
As mentioned, carrier synchronization and symbol
synchronization needs to estimate the phase of synchronous signal
which can be realized by using a PLL. Frame synchronization is
realized in a different wayinserting frame alignment signal
(distinctive bit sequence). Therefore, the basic task of frame
synchronization is how to detect the alignment symbol.
Besides add frame alignment bits, some code such as self-
synchronizing code can be synchronized without adding extra bits. In
this section, we only focus on the first method inserting frame
alignment signal.
2011.11
Frame Synchronization

Bunched frame alignment signal
Distributed frame alignment signal
Start-stop Method
1. Start-stop method
It is widely used in teleprinter. Each symbol contains 5-8 data bits, a start bit and
a stop bit.
start bit "0" width
stop bit: "1", width
System will keep sending stop bit when it is idle. When "1" "0", the receiver will
start to receive a data symbol.
b
b
T
T >

Drawbacks:
1). Low transport efficiency
2). Low precision of timing
Start-stop Method
Bunched frame alignment signal
2. Bunched frame alignment signal
This method inserts synchronous code at a particular place in
each frame. The code should have a sharp self-correlation function.
The detector should be simple to implement.
Frame synchronization code: Barker code, optimal synchronous
code and pseudo-random code.
( )
{ }
( )
1 2 3
1
1 Barker code
A n bits barker code , , , its self-correlation function
satisfies
0
0or 1 0
0
n i
n j
x i i j
i
x x x x x
n j
R j x x j n

+
=
=
= = < <

=+1 or -1.

Barker code is not a periodic sequence. It is proved that when 12100, we can only
find barker code with 2, 3, 4, 5, 7,11,13.
j n
n
n

>

<
=
Barker Code
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n barker code
2 + +
3 + + -
4 + + + - + + - +
5 + + + - +
7 + + + - - + -
11 + + + - - - + - - + -
13 + + + + - - + + - + - +

Barker Code
2011.11
( )
( )
1 1 2 2 7 7
1 2 2 3
Example A barker code with 7 find its self-correlation function
0: 0 7
1: 1 0
Similarly, we can determine .
The result is shown below, we can see it has a shar
x
x
x
n
j R x x x x x x
j R x x x x
R
=
= = + + + =
= = + + =

(j)
p peak when j 0. =
Barker Code
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(2) Barker code generator
shift register

Examplewhen n=7, a 7 bits shift register. The initial state is a barker code.
Barker Code
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(3) Barker code detector
Barker Code
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1
: "1"
1
1
: "0"
1
If the output connection of the shift register is the same with a barker code then
input
input
+

The barker code detector follows:

output "1":?

output "0":?

output "1":?

output "0":?

when the input is a barker code, the output of the shift register is "1111111". The
detector will send a synchronous impulse.
Barker Code
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Distributed frame alignment signal
3. Distributed frame alignment signal
The synchronous code is distributed in the data signal. That means
between each n bits, a synchronous bit is inserted.
How to design synchronous code:
1. Easy to detect. For example: 11111111or 10101010
2. Easy to separate synchronous code and data code. For example: In some
digital telephone systemall 0 stands for ring, so synchronous code can
only use 10101010.
To determine the synchronous code, receiver need to detect the code bit by
bit. Generally, the code can be detected by shifting the signal code by code.
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Distributed frame alignment signal

2011.11
Exampledata code is all 0synchronous code is all1
The synchronous code is generated by frequency division (N=4)of the
symbol synchronous impulse (a). In practical system, the local code (d) will
not be exact the same with (c).Therefore, the output of the XOR gate will
have nonzero waveform (e). After one bit delay (f), the exclusion gate will
discard one symbol synchronous impulse (b). By repeating this procedure,
finally (d) and (c) will be exactly the same, frame synchronization is realized.
Distributed frame alignment signal
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Performance
Performance of frame synchronization system
Bunched frame alignment signal
1. Probability of missing synchronization P
L
Affected by noise, the detector may not be able to detect the
synchronous code. The probability of this situation is called probability of
missing synchronization P
L
.


Assume the length of synchronous code is nbit error rate is Pe. The
detector will not be able to detect if more than m bit errors happen, then:
( )
0
1 1
m
n x
x x
L n e e
x
P C P P

=
=

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2. Probability of false synchronization P
F
Since data code can be arbitrary, it may be the same with synchronous code.
The probability of this situation is called probability of false synchronization P
F
.
P
F
equals to the probability of appearance of synchronous code in the data code.
a. In a binary code, assume 0 and 1 appears with the same probability. There are 2
n

combinations of a n bit code.

b. Assume when there are more than m bit errors, the data code will also be detected
as synchronous code.
Performance
0
1
When 0 only 1( ) code will be detected as synchronous code
When 1 there are codes will be detected as synchronous code;
......
Therefore the probability of false synchronization is:
n
n
x
n
x
F
m C
m C
C
P
=
=
=
=

m
0
0
1
2 2
m
n
x
n
n
x
C
=
| |
=
|
\ .

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Performance
L L F
P and P depends on the length of synchronous code n and the maximum bit error m.
When n , P P when m , P P
L F
F
| + | | + |
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s
L
3. Average build time t
Assume both P and P will not happen the worst case is we need one frame to
build frame synchronization. Assume each frame contains N bits, each bit has a width
T , then one f
F
b

( )
b
b
1
s
rame costs NT .
Now assume a missing synchronization or a flase synchronization also needs NT
to rebuild the synchronization, then:
1
Bisedes, the average build time of using the dis
b L F
t NT P P = + +
( )
2 2
1 2
s
tributed frame alignment signal is:
1
Apparently, , so the previous method is more widely used.
s b
s
t N T N
t t
= >>
<
Performance