System Spec

Architecture
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Setup and Hold
Digital Systems Timing
Conventions
All digital systems need a convention about when a
receiver can sample an incoming data value
Synchronous systems use a common clock
asynchronous systems encode data ready signals alongside, or encoded
within, data signals.
Also need convention for when its safe to send another value
synchronous systems, on next clock edge (after hold time)
asynchronous systems, acknowledge signal from receiver

Large Systems
Most large scale ASICs, and systems built with these
ASICs, have several synchronous clock domains
connected by asynchronous communication channels


Clocked storage elements
Transparent Latch, Level Sensitive
data passes through when clock high, latched when clock low








D-Type Register or Flip-Flop, Edge-Triggered
captured on rising edge of clock, held for rest of cycle

Race
1 0 0
1
1
Off
1 0 0
1
1
Off
0 1 1
0
0
0
Off
Off
So what is race to do with Setup
and Hold?
Setup represents the race for new data to Propagate
around the feedback loop before clock closes the
input gate.
If data arrives too close to clock edge, it wont set up
the feedback loop before clock closes the input
transmission gate.
Hold time represents the race for clock to close the
input gate before next cycles data disturbs the
stored value.
If data changes too soon after clock edge, clock might
not have had time to shut off input gate and new data
will corrupt feedback loop.
Flip-Flop

On positive edge, master latches input D, slave
becomes transparent to pass new D to output Q

On negative edge, slave latches current Q, master
goes transparent to sample input D again
Latch Parameters
t
c-q
t
d-q
D1
Q
t
pmax
D2
max
D1
Clk
Q D2
Clk
Q t
pmin
/t
pmax
D2
min
t
pmin
t
su
t
hold
Clk
T

Clk
Latch Timing Parameters
T
CQmin
/T
CQmax
Propagation inout when clock opens latch
T
DQmin
/T
DQmax
Propagation inout when transparent

T
setup
/T
hold
Define window around closing clock edge during which data must be steady
to be sampled correctly
Flip-Flop Parameters
D1
Clk
Q
D2
Clk
Q
t
pmin
/t
pmax
D1
t
c-q
Q
Clk
T

t
su
t
hold
Clk
t
pmax
t
pmin
D2
max
D2
min
Flip-Flop Timing Parameters
T
CQmin
/T
CQmax
Propagation inout at clock edge
T
DQmin
/T
DQmax
??!!!????
T
setup
/T
hold
Define window around rising clock edge during which data must be
steady to be sampled correctly
Setup and Hold
Setup :
Data should be fast enough so as to reach the capture
flop/latch before the next clock edge.
That is how slow data can afford to be
Hold :
Data should be slow enough so as not to reach the capture
flop/latch at the same clock edge.
That is how fast data can afford to be
Choice of Path
X
An Example
T
CQ
= 0.5ns
T
setup
= 1ns
T
hold
= 2ns
T
ClkMin
=

D1
Clk
Q
D2
Clk
Q
T
p
= 3ns
T
p
= 0.2ns
T
CQ
+ T
p
+ T
setup
= 3ns + 0.5ns + 1ns = 4.5ns

Single Clock Edge Triggered
Design
Slow path Timing Constraints
T
cycle
T
CQmax
+ T
Pmax
+ T
setup

can always work around slow path by using slower clock
Fast Path Timing Constriants
T
CQmin
+ T
Pmin
T
hold
bad fast path cannot be fixed without redesign!
might have to add delay into paths to satisfy hold time

Slack Borrowing in Latches
Transparent state of Latches allows time to be borrowed from the
previous cycle.
Clock Skew
Flip-Flop Parameters
D1
Clk
Q
D2
Clk
Q
t
pmin
/t
pmax
D1
t
c-q
Q
Clk
T

t
su
t
hold
Clk
t
pmax
t
pmin
D2
max
D2
min
t
skew
T
setup-
slack
T
hold-
violation
Flip-Flop Parameters
D1
Clk
Q
D2
Clk
Q
t
pmin
/t
pmax
D1
t
c-q
Q
Clk
T

t
su
t
hold
Clk
t
pmax
t
pmin
D2
max
D2
min
-t
skew
t
setup-violation
T
hold-
slack
Single Clock Edge Triggered
Design with SKEW
Slow path Timing Constraints
T
cycle
T
CQmax
+ T
Pmax
+ T
setup

-

T
skew
can always work around slow path by using slower clock
Fast Path Timing Constriants
T
CQmin
+ T
Pmin
T
hold
+

T
skew


bad fast path cannot be fixed without redesign!
might have to add delay into paths to satisfy hold time