(1)

Introduction to Verilog HDL

By-
Abhinav Vishnoi
Assistant Professor
Lovely Professional University
(2)
Verilog
What is Verilog HDL?
Verilog HDL is a hardware description language that
can be used to model a digital system at many levels
of abstraction ranging from
Algorithm Level
Gate Level
Switch Level

(3)
Verilog
Design Styles
Behavioral Design
Dataflow Design
Structural Design
Mixed Design
History
-The verilog HDL was developed by Gateway Design
Automation in 1983
-The language was placed in the public domain in 1990
-Open Verilog International (OVI) was formed to promote
verilog.


(4)
Verilog Features
Primitive Logic Gates and, or, nand
It provides flexibility in programming because of
USER-DEFINED PRIMITIVES (UDP)
Switch Level modeling primitive gates PMOS,
NMOS, CMOS,RPMOS,RNMOS,RCMOS
Explicit language constructs are provided for
specifying pin-to-pin delays, path delays and timing
checks of a design
(5)
Traditional vs. Hardware Description
Languages
Procedural programming languages provide the how or
recipes
for computation
for data manipulation
for execution on a specific hardware model
Hardware description languages describe a system
Systems can be described from many different points of
view
Behavior: what does it do?
Structure: what is it composed of?
Functional properties: how do I interface to it?
Physical properties: how fast is it?



(6)
Usage
Descriptions can be at different levels of abstraction
Switch level: model switching behavior of transistors
Register transfer level: model combinational and
sequential logic components

Descriptions can used for
Simulation
Verification, performance evaluation
Synthesis
First step in hardware design

(7)
Why do we Describe Systems?
Design Specification
unambiguous definition of components and interfaces
in a large design
Design Simulation
verify system/subsystem/chip performance prior to
design implementation
Design Synthesis
automated generation of a hardware design


(8)
Design process
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds..
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Specification
Verilog HDL description (Your Verilog HDL Source
Files)
Functional simulation
Synthesis
(9)
Design process (2)
Configuration
Timing simulation
On chip testing
(10)
Alternatives
The Verilog hardware description language
Finding increasing use in the commercial world
SystemVerilog gaining prominence
VHDL dominates the aerospace and defense worlds

Programming language based design flows
SystemC
C++ with additional hardware-based language elements
C-based design flows
C + extensions as well as ANSI C based
Other
Java, MATLAB, and specialized languages
(11)
Role of Verilog HDL








Verilog HDL
System description and documentation
System simulation
System synthesis

(12)
Simulation Tools
(13)

Logic Synthesis

Verilog HDL description
Circuit netlist
module bitwise(a,xnr,b,nt,xr,an,ors);
input [3:0]a,b;
output [3:0]nt,an,ors,xnr;
output [3:0]xr;
assign xr[0]=a[0]^b[0];
assign xr[1]=a[1]^b[1];
assign xr[2]=a[2]^b[2];
assign xr[3]=a[3]^b[3];
assign xnr[0]=a[0]~^b[0];
assign xnr[1]=a[1]~^b[1];
assign xnr[2]=a[2]~^b[2];
assign xnr[3]=a[3]~^b[3];
assign an[3:0]=a[3:0]&b[3:0];
assign ors[3:0]=a[3:0]|b[3:0];
assign nt[3:0]=~a[3:0];
endmodule

(14)
Synthesis Tools

(15)
Implementation
After synthesis the entire implementation process is
performed by FPGA vendor tools

(16)
Implementation