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Design
Evelyn Grossara, Michele Stucchi,
Karen Maexa and Wim Dehaenea
ISQED 2006
San Jose, CA, USA
© imec 2006
Outline
Introduction
Statistically-Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions
Icrit
Distributions of frequency
and standby leakage current
Id,sub Vth (Isb) in microprocessors
(0.18um)
significant parameter variations
[Borkar, DAC’04]
(Vth, Id,sub) from device to device
Introduction
Statistically-Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions
BLB wl
Vdd
PUP1 PUP2
wl
Vdd
BL
Read current of weakest
1 0 SRAM cell mainly limits the
PG1 VL VR PG2 delay constraint
PDN1 PDN2 (first order approximation)
gnd
VBLdd->0V
SRAM cell is most vulnerable VBLB
dd V
Vdd
dd PUP1 PUP2 V
Vdd
dd
to noise during read operation 10 0
1
PG1 VL VR PG2
V Vwldd V PDN1 PDN2
Vdd wldd
BLB
+Vn- inv1
dd BL
VL1 0
VR
gnd
1.5
-Vn VL
VR
1
VR
0.5
Constraint algorithm:
selects SRAM cell design which fulfills the delay and
functionality (read stability and write-ability) constraints
0 0
BLB wl
Vdd wl
Vdd
BL
only sub-threshold
PUP1 PUP2 Vdd
Vdd
0 1 leakage current (Ids,sub) is
PG1 VL VR PG2 considered, due to
Ids,sub ~ exp(Vth)
PDN1 PDN2
gnd
Introduction
Statistically Aware Optimization
Model distributions of performance parameters
Statistical sensitivities
Results
Conclusions
Introduction
Statistically Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions
Statistical sensitivity
gives information about direction and magnitude in which the
design parameter W has to move to improve the yield of the
design, which depends on the Vth intra-die variations
70
49.5% fulfills 100
60 the Wpg
SNM constraint Wpup
50 Wpdn
of 120mV for 80
Frequency
40 W pg=190nm
0
0.09 0.1 0.11 0.12 0.13 0.14 0.15
SNM [V] 70 20
60
29.8% fulfills 0
50 1.9 2 2.1 2.2 2.3 2.4
the SNM Transistor Width [m] -7
x 10
Frequency
constraint of
40
120mV for
30 W pg = 200nm
20
10
0
© imec 2006 Evelyn Grossar-TAD- 0.09 0.1 0.11 0.12 0.13 0.14 0.15 11
SNM [V]
Outline
Introduction
Deterministic Method for SRAM Cell Optimization
Stability, delay and leakage power definition
Deterministic optimization approach
Worst-Case optimization approach
Results
Statistically Aware Optimization
Modeling the distributions of the performance parameters
Statistical sensitivities
Results
Conclusions
1.75
with the worst-case approach
1.7
Iread Target Actual Iread Area
1.65
100uA 17% 27%
1.6
ca. 12%
ca.14% 170uA 10% 11%
1.55
1.45
1 1.2 1.4 1.6 1.8 power SRAM cell results in 40%
Iread Target [A]
read current improvement
-4
x 10
© imec 2006 Evelyn Grossar-TAD- 13
Outline
6
Iread Target = 130uA, SNM Target = 120mV, Vwrite Target = 0.4Vdd
3.5 x 10
worst-case approach
statistical approach
Total standby leakage power
distribution for an array matrix
3
1.5
1
Central Limit Theorem states
0.5 that the sum of independent
0
identical distributions of any
1.7 1.75 1.8 1.85 1.9 1.95
Total standby leakage power [W]
2 2.05
x 10
-4 type approaches a normal
distribution
+
p1 p2
- sets all Vth parameters (p1, p2) to their worst-case value
with respect to the performance parameter
- overestimation of the underlying process variations
- increased power consumption and area
Delay constraint
Vdd
of SRAM cell:
BLB wl
Vdd
PUP1 PUP2
wl
Vdd
BL
Read current of weakest
1 0 SRAM cell mainly limits the
PG1 VL VR PG2 delay constraint
PDN1 PDN2
(first order approximation)
gnd
© imec 2006 Evelyn Grossar-TAD- 17