Memories I

Dr. T.Y. Chang

NTHU EE
2007.11.20_22_27

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MI-1
 Contents
 Introduction
 SRAM
 DRAM
 Mask ROM
Sedra/Smith V.5 Chapter 11

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MI-2
 Memory Types
 Main Memories
 Fast
 Random Access

 High-performance

 Mass Storage Memories

 Mass storage
 Low-cost

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MI-3
 Memories Classifications (Neamen)
 Random Access Memories (RAMs)
 Volatile: lose data when power off
 Search

 Content-Addressable Memories (CAMs)

 Store data
 Static RAM (SRAM)
 Faster, 6 Trs/cell
 Dynamic RAM (DRAM):
 High Density, 1 Tr and 1C per cell, need ref
resh
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MI-4
 Memories Classifications
 Read-Only Memories (ROMs)
 Nonvolatile: retain data even power off
 Store OS, fixed data
 Field Programmable Memories
 Nonvolatile
 EPROM, EEPROM, FPGA, Flash, FRAM

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MI-5
 Memory Architecture (Neame
n)
 Inputs: Address lines, Data line(s), R/W con
trol, Enable (Optional)
 Output: data line(s)

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MI-6
 RAM Architecture
 Decoder:
 N address lines
decode to 2N lines
 Only one selected
 Memory array
 Control circuit

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MI-7
 11.4.1 SRAM Cell
 Bit and Bit
 Word line
 Two inverters and two switches

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MI-8
 SRAM Read Operation
 B and B precharge to VDD/2 (or VDD)
 Assume V =0 and VQ= VDD
Q
 Switches on
 Ex 11.2

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MI-9
 SRAM Write Operation
 B and B charge to 0 and VDD, respectively.
 Assume V Q=0 and VQ= VDD
 Switches on

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MI-10
 DRAM
 Dynamic RAM
 One switch, one data line, and a Cap
 Fresh required (refresh)

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MI-11
 SRAM Sense Amplifier
 Usually, 1 SA/col.
 SA off if Φs=0
 Before Read opr,
ΦP=1 → B= =V
DD/2;
 then ΦP=0, WL=
1
 then Φs=1

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MI-12
 SRAM SA Functions

VDD
vB   V (1)e (Gm / C B ) t
2
VDD
vB   V (0)e (Gm / CB ) t
2

 In R1, the sense amplifier causes the initial small

increment V(1) to grow exponentially to VDD.
 In R0, the negative V(0) grows to 0.
 Complementary signal waveforms develop on the B a
nd Blines.
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MI-13
 Ex. 11.3 in p 1041
 Given (W/L) ratios and other information
to find rise/fall time in SRAM cell.

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MI-14
 DRAM SA
 Dummy cell required

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MI-15
 Row-Address Decoder
 Only one row is selected

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MI-16
 Column-Address Decoder I
 Two types:
 Pass-Transistor Multiplexer

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MI-17
 Column-Address Decoder II
 Tree decoder

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MI-18
 Read Only Memory
 MOS ROM
 Mask Programmable ROM
 Final step(s) for connections in Fabrication
 Programmable ROM
 PROM
 EPROM
 EEPROM

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MI-19
 MOS ROM
 8 words x 4 bits (32 bits)

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MI-20
 Problems (Not HW)
 For a 1Mx1 RAM, how many address
lines are required?

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MI-21
 Decoder (Neamen)

=(a4+a3+a’2+a’1+a0)’
= a’4a’3a2a1a’0
=(00110)

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MI-22
 SRAM Cells: NMOS (Neamen)

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MI-23
 CMOS SRAM Cell with pull-up

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MI-24
 Read Operation
 IMNA(S)<IMN1(T) (IMNB(S)<IMN2(NS))
 KnA(VDDQVTN)2<KN1[2( VDD VTN )Q Q2]; & Q=VTN
 (W/L)nA/(W/L)n1< [2(VDD VTN) 3V2TN] /(VDD 2VTN )2
 VDD =3, VTN =0.5
(W/L)nA/(W/L)n1<0.56

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MI-25
 Write Operation
 IMp2(S)<IMNB(T) (IMP1(S)<IMNA(T))
 Kp2(VDD+VTP)2<KNB[2( VDD VTN )Q’ Q’2]; & Q’=VTN
 (W/L)p2/(W/L)nB< (k’n/k’p)[2(VDDVTN)3V2TN] /(VDD +VTp )2
 VDD =3, VTN =0.5, VTP =  0.5, then (W/L)p2/(W/L)nB<0.72

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MI-26
 SRAM R/W Circuitry

Vo

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MI-27
 Write

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MI-28
 DRAM Cell
 Logic-0 = 0 V
 Logic-1= VDD  VTN

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MI-29
 DRAM Operations
 Dummy Cell CR=0.5 CS
 Init: VCR=0, 2=1 Precharge, CEbar=1
 Read: 2=0, CEbar=0, charge redistrib.
& D-WL=RowSel WL=1
 R0: V1<V2
 R1: V1>V2

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MI-30
 ROM
 Mask ROM
 Select Y
 Select X
 Q  Vo=0
 No Q  Vo=1

0110
1000
0101
1010

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MI-31
 PROM (Neamen)
 Large current
 to blow out fuse
 to connect by anti-
fuse
 Blow fuses by user
 Select X
 Select Y
 Vo= 0 fuse exits
 Vo= 1 No fuse

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MI-32
 EPROM

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MI-33
 EPROM
 Floating gate

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MI-34
 EPROM I-V Characteristics
 Floating gate

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MI-35
 EPROM During Programming

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MI-36
 EPROM Program and Erase

Ref. Book: D.A. Hodges, H. G. Jackson, R. A. Saleh,

"Analysis and Design of Digital Integrated Circuits,"
3rd Ed., McGraw Hill, 2004. Chapter 9.

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MI-37
 EEPROM

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MI-38