8051 AND ADVANCED PROCESSOR

ARCHITECTURES
01: 8051 microcontroller
architecture
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1
The Structural Units in a Processor:
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The Structural Units in a Processor:
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Buses
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1) Internal and external buses
interconnect the processor
internal units with the external
system memories, I/O devices
and all other system elements
2) Address, data and control
buses
MDR, MAR, BIU , PC and SP
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3) MDR (memory data register) holds
tMDR, MAR, BIU, PC and SP A and the
accessed byte or word
4) MAR (memory address register)
holds the address
5) BIU (Bus Interface Unit)
6) Program Counter or Instruction
Pointer and
7) Stack Pointer
Registers
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8) ARS (Application Register Set): Set of
on-chip registers for use in the
application program. Register set -also
called file and associates an ALU or FLPU.
9) Register window- a subset of registers
with each subset storing static variables
and status words of a task or program
thread. Changing windows help in fast
context-switching in a program.
ALU, FLPU
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10) ALU and FLPU (Arithmetic and
Logic operations Unit and Floating
Points operations Unit). FLPU
associates a FLP register set for
operations.
Caches
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12) Instruction, Data and Branch Target Caches and
associated PFCU (Prefetch control unit) for pre-
fetching the instructions, data and next branch
target instructions, respectively.
Multi-way CacheExample- 16 kB, 32-ay
Instruction cache with 32 byte block for data and
16 kB in ARM
Cache block Enables simultaneous caching of
several memory locations of a set of instructions
System Definition
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8051 microcontroller features
12 MHz clock. Processor instruction cycle time
1 [in Classic version]
An 8-bit ALU.
Harvard memory architecture the external
program memory and data memory have
separate address spaces from 0x0000 and
separate control signal(s).
8-bit internal data bus width and 16-bit internal
address bus Harvard memory architecture
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8051 microcontroller features (contd.)
CISC (Complex Instruction Set Computer).

Special function registers (SFRs) PSW
(processor status word), A (accumulator), B
register, SP (stack pointer) and registers for
serial IOs, timers, ports and interrupt handler.
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8051 microcontroller features (contd.)
Special bit manipulation instructions.

16-bit Program counter with initial default
reset value defined by processor is 0x0000.

8-bit stack pointer with initial default value
defined by processor is 0x07
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8051 microcontroller features (contd.)
Classic 8051 simple architecture
no floating-point processor,
no cache,
no memory management-unit,
no atomic operations unit,
no pipeline and
no instruction level parallelism.
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8051 microcontroller features (contd.)
on-chip RAM of 128 bytes. [8052-version RAM
256 bytes.]
32 bytes of RAM also used as four banks
(sets) of registers. Each register-set (bank)
thus eight registers.
External data/stack memory can be added up
to 64 kB in most version. In certain 8051
enhancements, this limit enhanced to 16 MB
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8051 microcontroller features (contd.)
8351 version on-chip ROM, 8751 version
EPROM, 8951 version has on-chip EEPROM or
flash memory of 4 kB.
Several versions provide for higher capacity
ROM. Additional program memory can be
added externally upto 64 kB. In extended 8051
and unified address space versions (8051 EX
and MX versions), this limit has been
extended to 16 MB.
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Two external interrupt pins, INT0 and INT1.
Four ports of 8-bits each in single chip mode.
Two timers
Serial interface (SI)programmable for three
full duplex UART modes for serial IO. [IO with
each bit of a word successive transmission on
the data line for a time interval.] The same be
programmable for half duplex synchronous IO
8051 microcontroller features (contd.)
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8051 microcontroller features (contd.)
In certain versions DMA controller
In certain versions pulse width modulator
and thus support to DAC, d.c. and servo motor
controls.
In Certain versions modem, watchdog timer,
ADC. Siemens SAB 80535-N supports ADC with
programmable reference voltage. Advanced
versions support these features and a version
is selected as per the system requirement
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2. 8051
microcontroller
instruction set
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Data Transfer Instructions
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Bit and Byte Manipulations and Logic
instructions
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Arithmetic Instructions
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Program Flow Control Instructions
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Interrupt Flow Control Instructions
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learnt
8051 architecture

Instruction set of 8051
Summary
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8051 IO ports, Circuits
and IO Programming and External
Memory Circuits
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1. IO PORTS
Ports P0 and P1 pins and alternative functions.
P0.0 P0.1 P0.2
P0.3 P0.4 P0.5
P0.6 P0.7
Also as
AD0- AD7

Lower
address bits
cum data bus
P1.0 P1.1 P1.2
P1.3 P1.4 P1.5
P1.6 P1.7
Also P1.6 as
I
2
C clock, P1.7
as I
2
C serial
data, and P1.0
and P1.1 for T2
(8052)
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Ports P2 and P3 pins and alternative
functions
P2.0 P2.1 P2.2
P2.3 P2.4 P2.5
P2.6 P2.7
Also as
A8- A15
Higher address-bits
bus
P3.0 P3.1 P3.2
P3.3 P3.4 P3.5
P3.6 P3.7
Also
RxD/SyncData,
TxD/SyncClk,
INT0/GT0,
INT1/GT1, T0,
T1, WR, RD
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B. IO Circuits
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IO port circuit for two stepper motors in
a printer
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IO port circuit for six servo motors
in a robot
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C. IO Byte Programming
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Port Byte Programming
8051 internal IO ports P0, P1, P2 and P3 byte
addresses used to access and perform read or write
or other operations
Direct 8-bit addresses of each are specified in the
instructions
Addresses of bytes at P0, P1, P2 and P3---- 0x80,
0x90, 0xA0 and 0xB0
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Example.1
MOV 0xA0, #0xFF moves bits to port P2 and
P2 bits will become = 11111111b.
MOV 0x90, #0x1C moves bits at port P1 =
00011100b.
After this instruction, INC 0x90 will make P1 =
00011100b + 1 = 00011101b.
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D. IO Bit Programming
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Bit Programming
Each port P0, P1, P2 and P3 8 bits and each bit has
addresses to access and perform read or write or other
operations using bit-manipulation instructions.
Addresses are the bit addresses. Each bit address is of
8-bits, which are specified in the instructions.
Bits P0.0 to P0.7 addresses ----- 0x80 to 0x87.
Bits P1.0 to P1.7 addresses -----0x90 to 0x97,
P2.0 to P2.7 ------ 0xA0 to 0xA7 and
P3.0 to P3.7 ------ 0xB0 to 0xB7.
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Bit Programming
All instructions in the instruction set using bit addresses can be
used to access and perform complement read or write or
other operations.
C flag in PSW ---- Accumulator for bit logic operations.
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Example.2
CPL 0x90 complements the bit 0 at port P1.
CLR 0x80 makes P0.0 as 0. Now after a
delay of period= T1, the SETB 0x80 will
make P0.0 as 1. Now after a delay of
period= T2, the CLRB 0x80 will make gain
P0.0 as 0.
A pulse of time-period T2 and duty cycle
100 T1/(T1 + T2) creates if the instructions
are executed in a loop.
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Example.2 (contd.)
SETB C will set carry bit in PSW to 1. After this
operation, ANL C, 0x93 will perform logic AND operation
between bits C and P1.3 and result will be in C. If P1.3 =
0 then C will become 0 else C will remain 1.

CLR C will reset (clear) carry bit in PSW to 0.
After this operation, ORL C, 0xB2 will perform logic OR
operation between bits C and P3.2 and result will be in
C. If P3.2 = 0 then C will remain 0 else C will remain 1.
After this operation, MOV 0x85, C will move result in C
to P0.5.
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E. External Memory and Port
Circuits
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Memory mapped IO
8051 Memory and ports assigned the
addresses such each have distinct range of
addresses in the data memory address
space.
Interfacing circuit design identical to that
for the memory connects the external
ports and programmable peripheral
interface (PPI).
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Connection to the external program
and data memory circuits
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Interfacing using external PPI port in
8051
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Port P0 used in expanded mode and ALE
AD0-AD7 the multiplexed signals of A0- A7 lower
address bits of the address bus and D0-D7 bits of data
bus.

A0-A7 and D0-D7 time division multiplexed. For an
interval, the processor activates ALE (address latch
enable) in an instruction cycle and the AD0-AD7 lines
have A0-A7 and a latch circuit separates A0-A7 signals
for the memory
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Harvard Memory Architecture
Two sets of memory--- program memory and data
memory.

Two control signals---- PSEN and RD to control read
from program memory or data memory.

Control signal ALE to control use of AD0-AD7 as
address or data at a given instance
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Port P2 expanded mode, PSEN and RD
A8-A15 address signals -----
When the processor activates PSEN (Program
store enable), it reads the byte from external
program memory through D0-D7 data bus.

When the processor activates RD (read), it reads
the byte from external data memory through D0-
D7 data bus.
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Addresses outside the internal RAM,
SFR and internal program memory when
control signal EA inactive
Then processor always accesses the external
memory whether EA active or not .
Internal RAM and SFR addresses between 0x00 and
0xFF are same as external data memory addresses
0x0000 and 0xFFFF.
Internal program memory addresses between
0x0000 to 0xFFF (in case of 4 kB internal ROM) are
same as external program memory addresses 0x0000
and 0xFFFF.
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Control signal EA
When a control signal EA activate ------
processor always accesses the
external addresses in memory
instead of internal memory or
register addresses
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Summary
View on
IO port Pins for P0, P1, P2, P3
IO port circuit examples
Examples of IO port byte programming
Examples of IO port bit programming
Memory mapped IO
Interfacing circuits to external memory or Port
Harvard memory external data and program memory
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F: Counters and Timers
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Timing and counting devices
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Two T0 and T1 in classic 8051 family
and three T0, T1 and T2 in 8052 family
(an extension of 8051).
Counting/timing device as timer
Counting/timing device as counteres
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A device for counting when the inputs
to count are given externally. Counter
is given the input to count from
external input pin.
A device for timing when the inputs to counting
are given by a clock. The clock pulses are
internally given at the specific time intervals in
case of functioning as timer.
Counting/timing device External controls
for activation or deactivation of running
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When timing or counting devices is
externally controlled by the gate input,
when GT0 or GT1 is externally activated
the device can function else it deactivates
in gate input mode.
GT0 or GT1 signals are given
at P3.2 and P3.3.
Counting/timing device External count
inputs in counter mode
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T0 counts the T0 is given the input to
count from external input pin T0 at P3.4.

T1 counts when T1 is given the input to
count from external input pin T1 at P3.5.
Four Port P3 Pin functions
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P3.2, P3.3, P3.4 and P3.5 When TMOD SFR
bits 3, 7, 2 and 6 set = 1, function as
GT0 (gate for starting/stopping T1),
GT1 (gate for starting/stopping T1),
T0 (count input to T0) and
T1 (count input to T1) inputs
respectively.
Two SFRs TH1-TL1
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For accessing the counts or time higher
and lower 8 bits of T1 device

The SFRs hold the T1-device 16-bits.
Two SFRs TH0-TL0
For accessing the count or time higher
and lower 8 bits
The SFRs hold the T0 device 16-bits
SFR TMOD
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Controls the T1 and T0 modes using the
upper and lower 4 bits each, which
program the counting/timing of T1 and T0.
A bit in each controls the function that
external gate input controls or not.
A bit controls the function that counter
or timer mode is used.
Two bits controls the functional mode of
timer/counter as mode 0 or 1 or 2 or some
other action
SFR TCON T1 and T0 control and
status bits
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Upper four 4 bits program the modes of
counting/timing devices T1 and T0.
TCON.7 and TCON.5 show the
timer/counter overflow status for T1 and
T0 respectively.
TCON.6 and TCON.4 control the start
and stop of the timer/counter
Lower bits of TCON are for the interrupt
control for INT0 and INT1
Timer/Counter T0
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8-bit SFRs TMOD (lower 4 bits), TCON (bit 5
and 4), TL0 (count/time bits), TH0 (count/time
bits)
Counter with inputs at P3.4 when bit 2 TMOD
=1, timer with internal clock timed inputs when
bit 2 TMOD = 0
When mode set = 0, 8-bit timer/Counter
mode and TH0 is used and TL0 is used for
prescaling (dividing) inputs by 32
When mode set = 1, 16-bit timer/counter
mode with TH0-TL0 is used for timing or
counting
Timer/Counter T0
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When mode set = 2, 8-bit timer/Counter TH0
is used and TL0 is used for auto-reloading the
TH0 after timeout using a preset value at TL0

When mode set = 3, two 8-bit timer/Counters
mode TH0 and TL0 are independent 8-bit
timer/counter and T1 does not function.
Timer/Counter T1
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8-bit SFRs used TMOD (upper 4 bits),
TCON(bit 7 and 6), TL1 (count/time bits), TH1
(count/time bits)
Counter with inputs at P3.5 when bit 6 TMOD
=1, timer with internal clock timed inputs when
bit 6 TMOD = 0
When mode set = 0, 8-bit timer/Counter
mode and TH1 is used and TL1 is used for
prescaling (dividing) inputs by 32
When mode set = 1, 16-bit timer/counter
mode with TH1-TL1 is used for timing or
counting
Timer/Counter T1
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When mode set = 2, 8-bit timer/Counter TH1
is used and TL1 is used for autoreloading the
TH1 after timeout using a preset value at TL1
When mode set = 3, T1 stops as TH0 now
functions in place of T1.
Summry
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Learnt about
Timer-Counter T0 and T1
TMOD SFR
TCON SFR upper Four bits
External four P3 pins for external control and
external count inputs
Modes 0, 1, 2, 3 of T0
Mode 0, 1 and 2 of T1
G: Serial Data
Communication Input/Output
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Serial Interface SI
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programmable for
half duplex synchronous serial or
full duplex asynchronous UART mode
Two 8-bit SFRs
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SBUF (8 serial received bits or transmission
bits register depending upon instruction is using
SBUF as source or destination)

SCON (8-serial modes cum control bits
register) and SFR PCON.7 bit
SBUF
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Single SFR address for transmit and received
byte buffers when the serial output or input is
sent.
0x99 the address of SI buffers.
SFR holds the SI transmission 8-bits when it is
written.
MOV 0x99, A instruction writes A into
transmission buffer from A register
MOV R1, 0x99 instruction read R1s register
from the receive buffer
SCON
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SFR to control the SI interface.
Three upper bits programs the modes as 0 or
1 or 2 or 3.
Mode 0 is half duplex synchronous.
Modes 1 or 2 or 3 are full duplex
asynchronous modes.
Bit SCON.4 enables or disables SI receiver
functions.
SCON
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Two bits SCON.3 and SCON.2 specify
the 8th bit to be transmitted and 8th bit
received when the mode is 2 or 3. A bit
SCON.1 enables or disables SI transmitter
interrupts (TI) on completion of
transmission.
Bit SCON.0 enables or disables SI
receiver interrupts (RI) on completion of
transmission.
Mode 0 functions Input or output
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Depends upon instruction using SBUF as
source or destination
Synchronous serial mode data and clock
inputs, or
Synchronous serial mode data and clock
output
Mode 0 when SCON bits 7 and 6 (mode-
bits) are 00
Mode 1 Input or output
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10 bit (start plus 8- serial data plus stop
total 10 bits) UART mode serial input or
output
Input or output whether SBUF used for
read or write in instruction
Baud rate programmable using T1 or T0
timers (T2 in 8052)
Mode 1 when SCON bits 7 and 6 are 01
Mode 2 Input or Output
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Eleven bit (start plus 8- serial data plus
RB8 or TB8 bit plus stop total 11 bits)
UART mode serial input and output
Input or output whether SBUF used for
read or write in instruction
Fixed baud rate of (f/32) 12 or (f/64)
12Mbaud/s where f = crystal frequency
depending upon PCON 7 bit SMOD = 1 or
0, respectively
Mode 2 when SCON bits 7 and 6 are 10
Mode 3 Input or Output
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11 bit (start plus 8- serial data plus RB8
or TB8 bit plus stop total 11 bits) UART
mode serial input and output
Input or output whether SBUF used for
read or write in instruction
Baud rate with programmable using T1
or T0 timers (T2 in 8052)
Mode 3 when SCON bits 7 and 6 are 1,1
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Summry
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Learnt
Serial Interface functions
Half duplex synchronous serial mode 0
or
Full duplex asynchronous UART mode 1,
2or 3
SBUF
SCON
Hardware Interrupts of
8051
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Interrupt Sources
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External INT0 interrupt
T0 overflow interrupt
External INT1 interrupt
T1 overflow interrupt
SI serial UART or Synchronous mode
interrupt
SI synchronous serial mode interrupt
(separate in few families of 8051)
Timer 2 interrupt in 8052
SFR IE for interrupts enabling bits
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SFR to mask (disable) or unmask (enable)
the interrupts in 8051
Programming of SFR IE (Interrupt
Enable) register at address 0xA8 for the
byte or
Programming of IE using Bit addresses
0xA8 to 0xAF for the individual bits
SFR IP for interrupt priority bits
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Individual interrupt priorities set high or
low bits
Set priorities in IP override default
priorities for executing the ISRs
Byte address 0xB8 for the byte and at bit
addresses 0x88 to 0x8C or 0x8D or 0x8E
for the individual bits in the register, an
instruction can define that a given
interrupt is of higher (=1) or lower priority
(=0) among the various interrupts
8051 system Interrupt Features
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8051 permits when executing low-
priority ISR the in-between program flow
on interrupt to higher priority ISR
Permits masking all by a primary level
bit or individual sources by secondary level
bits by setting bits in SFR IE
Assigns default priorities
Permits overriding of default priorities
by setting bits in SFR IP
Vector Addresses
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An address from where either an ISR of
maximum 8-bytes executes or a Jump to a
programmed ISR starting address takes
place
When EA bit (primary level interrupt bit)
is set as well as specific interrupt bit
(secondary level interrupt bit) is set
External hardware Interrupts
INT0 and INT1
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programmable for
Two external interrupt pins, INT0 and
INT1 at P3.2 and P3.2 used for interrupt
P3.2 and P3.3 as pins for INT0 and INTI
external interrupt pins when bit 7 IE (interrupt
enable SFR) EA (enable all) bit is 1, and bits 0 and
2 are 1 and 1, respectively
Programmed by TCON lower 4 bits and
the IE register bits IE.2 and IE.0
INT1 and INT0 status bits
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Status bit TCON.3 for status of interrupt
at INT1
TCON.3 auto resets to 0 when ISR for
servicing INT1 interrupt starts.
Status bit TCON.1 for status of interrupt
at INT0 and
TCON.1 auto resets to 0 when ISR for
servicing INT0 starts.
INT1 and INT0 Edge or level type
control bits
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TCON.2 for type of interrupt at INT1 and is 1 if
it is edge-triggered type else 0.
TCON.0 for type of interrupt at INT0 and is 1 if
it is edge-triggered type else 0.
REAL WORLD INTERFACING -
Part 1
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1. Interfacing Using System Bus
Interfacing of processor, memory and IO devices
using memory system bus
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System bus interconnections for a simple
bus structure has three sets of signals
System bus defines by address bus, data-
bus, and control bus
A system-bus interfacing-design is according
to the timing diagrams of processor signals,
speed, and word length for instructions and
data.
Characteristics differ in the system
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Address Bus
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Processor issues the address of the
instruction byte or word to memory system
through the address bus.
Processor execution unit, when required,
issues the address of data (byte or word) to be
read or written using the memory system
through address bus.
The address bus of 32-bits used to fetch the
instruction or data from an address specified by
32-bit number.
EXAMPLE
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Let a processor at the start reset the program
counter at address 0. Then the processor issues
address 0 on the bus and the instruction at
address 0 is fetched from memory on reset
Let a processor instruction be such that it
needs to load register r1 from the memory
address M. The processor issues address M on
the address bus and data at address M is
fetched.
Data Bus
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Instruction fetch Processor issues the
address of the instruction, it gets back the
instruction through the data bus.
Data Read When it issues the address of the
data, it loads the data through data bus.
Data Write When it issues the address of the
data, it stores the data in the memory through
the data bus. A data bus of 32-bits fetches,
loads, or stores the instruction or data of 32-
bits.
EXAMPLE
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Processor issues address m for an instruction,
it fetches the instruction through data bus from
address m. [For a 32-bit instruction, word at
data bus from addresses m, m + 1, m + 2, and
m+ 3.]
Instruction executes for store of register r1
bits to the memory address M, the processor
issues address M on the bus and sends the data
at address M through the data bus. [For 32-bit
data, word at data bus sent to the memory
addresses M, M + 1, M + 2, and M + 3.]
Control Bus
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Issues signals to control the timing of various
actions during interconnection.
Signals synchronize all the subsystems.
address latch enable (ALE)[ Address Strobe (AS)
or address valid, (ADV)],
memory read (RD) or write (WR) or IO
read(IORD) or write,(IOWR) or data
valid(DAV)
Other control signals as per the processor
design.
Interrupts and DMA Control Signals
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Interrupt acknowledge (INTA) [on a request
for drawing the processor attention to an event]
INT (Interrupt) from external device interrupt
to the system
Hold acknowledge (HLDA) [on an external
hold request for permitting use of the system
buses]
HOLD when external device sends a hold
request for direct memory access (DMA).
EXAMPLE
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Processor issues the address, it also issues a
memory-read control signal and waits for the
data or instruction.
Memory unit must place the instruction or
data during the interval in which memory read
signal is active (not inactivated by the
processor).
EXAMPLE
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Processor issues the address on the address
bus, and (after allowing sufficient time for the
all address bits setup) it places the data on the
data bus, it also then issues memory-write
control signal (after allowing sufficient time for
the all data bits setup) for store signal to
memory.
Memory unit must write (store) the data
during the interval in which memory-write
signal is active(not inactivated by the
processor).
Interrupts and DMA Control Signals
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Interrupt acknowledge (INTA) [on a request for
drawing the processor attention to an event]
INT (Interrupt) from external device interrupt to the system
Hold acknowledge (HLDA) [on an external hold
request for permitting use of the system buses]
HOLD when external device sends a hold
request for direct memory access (DMA).
EXAMPLE
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Processor issues the address, it also issues a
memory-read control signal and waits for the
data or instruction.
Memory unit must place the instruction or
data during the interval in which memory read
signal is active (not inactivated by the processor).
EXAMPLE
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Processor issues the address on the address
bus, and (after allowing sufficient time for the
all address bits setup) it places the data on the
data bus, it also then issues memory-write
control signal (after allowing sufficient time for
the all data bits setup) for store signal to
memory.
Memory unit must write (store) the data
during the interval in which memory-write
signal is active (not inactivated by the processor).
Program memory access and data buses
multiplexed for memory access in
Harvard Architecture
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Address and data buses are multiplexed
Control signal PSEN active when accessing
program memory using the address and data
buses
Control signal Read or Write active when
accessing data memory using the address and
data buses
Time division multiplexed (TDM) address
and data bits for the memories
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TDM Different time slots, there are is a
different set sets (channel) of the signals.
Address signals during one time slot t. and data
bus signals in another time slot.
Interfacing circuit for the de-multiplexing of
the buses uses a control signal in such systems.
Time division multiplexed (TDM)
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address and data bits for the memories

Control signal Address Latch Enable (ALE) in
8051, Address Strobe (AS) in 68HC11 and
address valid (ADV) in 80196.
ALE or AS or ADV demultiplexes the address
and data buses to the devices
Interfacing circuit using Latch and decoders,
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ALE for latching the address
PSEN for program memory read using address
data buses
Each chip of the memory or port that
connects the processor has a separate chip
select input from a decoder.
Decoder is a circuit, which has appropriate
signals of the address bus at the input and
control circuit signals to generate corresponding
CS (chip select) control signals for each device
(memory and ports)
Interfacing- circuit
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Consists of latches, decoders and de-
multiplexers
Designed as per available control signals and
timing diagrams of the bus signals.
Circuit connects all the units, processor,
memory and the IO device through the system
buses.
Also called glue circuit used as it joins the
devices and memory with the system bus and
processor
Can be designed using a GAL (generic array logic)
or FPGA
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2. Interfacing Using System and IO Buses
System Bus and IO Bus
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System bus interconnects
Processor
memory systems and
subsystems
Another set of signals called I/O bus
Interfacing of processor with system bus at
first level and IO bus at second level
Popular IO buses and wireless communication
PCI Bus interfaces to devices designed to
meet the PCI standard.
USB interfaces
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2. Interfacing Using System and IO Buses
System Bus and IO Bus
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System bus interconnects
Processor
memory systems and
subsystems
Another set of signals called I/O bus
Interfacing of processor with system bus at
first level and IO bus at second level
3. Multilevel Buses
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4. Addresses of Ports and Devices in
Real World Interfacing
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Device Control Register, Status Register,
Receive Buffer, Transmit Buffer
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Each I/O device is at a distinct address or
set of addresses
Each device has three sets of registers data
buffer register(s), control register(s) and
status register
Device Addresses
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Device control and status addresses and port
address remains constant and are not re-
locatable in a program as the glue circuit
(hardware) to accesses these is fixed during the
circuit design.
There can be common addresses for input
and output buffers, for example SBUF in 8051
The processor, memory, devices Glue Circuit
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The processor, memory and devices are
interfaced (glued) together using a
programmable circuit like GAL or FPGA. The
circuit consists of the address decoders as per
the memory and device addresses allocated and
the needed latches multiplexers/demultiplexers
Device Addresses
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There may be common addresses for control
and status bits
There can be a control bits, which changes
the function of a register at a device address
Example
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Serial line device addresses of device
registers
Fixed by its hardware configuration of UART
port interface circuit in a of a system employing
80x86 processor. .
0x2F8 to 0x2FE at COM2 COM1 in IBM PC
Feature of UART serial line device in PC
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Two I/O data buffer registers (one for receiving
and other for transmitting) at a common address,
0x2F8
Data of two bytes of Divisor Latch are at the
distinct addresses, 0x2F8 (LSB) and 0x2F9 (MSB)
Three Control Registers of the device are at
three distinct addresses 0x2F90x2FA,0x2FB and
0x2FC.
Three Status Registers of the device are at
three distinct addresses 0x2FA, 0x2FD and 0x2FE
Feature of UART serial line device in PC
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Two I/O data buffer registers (one for receiving
and other for transmitting) at a common address,
0x2F8
Data of two bytes of Divisor Latch are at the
distinct addresses, 0x2F8 (LSB) and 0x2F9 (MSB)
Three Control Registers of the device are at
three distinct addresses 0x2F90x2FA,0x2FB and
0x2FC.
Three Status Registers of the device are at
three distinct addresses 0x2FA, 0x2FD and 0x2FE
Device Addresses
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Processor accesses device registers and
buffer registers from allocated addresses for
the Ports and Devices
Device Addresses
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Processor accesses device registers and
buffer registers from allocated addresses for
the Ports and Devices