THE POWER DISSIPATION COMPARISION

OF
DIFFERENT ALU ARCHITECTURES






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TALK FLOW
General Idea
Introduction
Basic ALU structure
ALU Design
ALU Architectures
Simulation results & Discussions
Conclusions
Referrences



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GENERAL IDEA
Low power is a challenging work in processor design.

Implementing power optimization on all component of the
processor is a choice.

ALU s architecture has several implications on power
consumption, delay and area.

With most power effective architecture we can save power
ranging from 19.38% to 33.87% and corresponding area
saving ranges from 14.92% to 56.37%

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INTRODUCTION
Battery powered and handheld devices such as laptop,tablet pc,cell
phones have improved our daily life greatly

I. Fast and multifunctional
II. Portability (Min Battery Weight,Max operating time)

Designer required to develop circuit and system that uses less
energy without sacrificing the performance.

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Power optimization can be fulfilled at different levels
with different methods s.a

Dynamic voltage scaling(DVS) at system level
Bus-coding at algorithm level.
Clock-gating and operand isolation at RTL(register
transfer level).
Transistor sizing and threshold voltage scaling at circuit
and transistor level.


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BASIC STRUCTURE






1. Clocked at highest speed.
2. Kept busy almost 100% of time.
3. ALU is most power hungry component.
So low power design of ALU can considerably reduce the total power
consumtion of a processor.







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ALU combines a variety of arithmetic and logic operations into a
single unit. (+,-,*,/,&,|,^)
Proper choice of ALU architecture is needed when the design is
targets for low power dissipation.
There are three typical ALU architectures
a) Complex structure.
b) Adder independent structure.
c) Chain structure.
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ALU DESIGN
All instructions performed can be accomplished through basic
operations.

An 8-bit ALU design is taken into consideration for the three
architectures.

Table shows function of designed ALU.

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Adder is most basic component of arithmetic circuit.
Ripple carry adder ---- 0(n) time,0(n) area adder.
Carry look ahead adder ---- 0(logn)time,0(nlogn) area adder
More popular due to speed & modularity.
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RIPPLE CARRY ADDER
CARRY LOOK AHEAD ADDER
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Relationship of inputs and outputs of an adder can be expressed as :-





For an N bit adder , carry look ahead adder speeds up addition operation by
eliminating the ripple delay and is given by formula :


This formulae is effective for N<=4.






So to design 8-bit addder of ALU two 4-bit CLAs are used



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ALU ARCHITECTURES :
1) COMPLEX STRUCTURE:
It combines a variety of arithmetic & logic operations into a single unit and
uses several control signals to choose the desired operation.
Logic operation is accomplished by modifying P and G block of the adder.
s0,s1,s2,s3 are signals which controls the function of P G block.
Signal c decides whether ALU should perform arithmetic or logic operation.




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For 8-bit adder of ALU, two 4-bit ALU is connected serially.


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(2) ADDER INDEPENDENT STRUCTURES:


It uses an adder that performs arithmetic operation & an individual module
that performs logic operation.
Individual block performs logic operations & CLA adder performs arithmetic
operations.













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For low power consideration, operand isolation technology is adopted.
Two AND gates are added after the two operands shown by the dotted
line.








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(3)CHAIN STRUCTURE:
It organizes a set of components as a chain & each component is responsible for
one type operation.
It has smaller area and is faster than tree structure
Placing a functional component differently in the chain structure may cause
different power consumption.
Different functional components placement to benchmark dhrystone , and get
the most power efficient one.
For low power consideration operand isolation technology is used.
Two de-multiplexers are added after the two operands.


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SIMULATION RESULTS AND DISCUSSIONS
Power consumption of different ALU architectures are compared.
ALU is designed using Verilog HDL code for functional simulation,
It is synthesized by Synopsys design compiler with SMIC 0.18um
standard cell library & then the power is calculated by Synopsys prime
power.

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COMPARING COMPLEX STRUCTURE AND
ADDER INDEPENDENT STRUCTURE
CLA in adder independent structure needs an AND gate & a XOR gate to
generate P G signals.

The adder also requires a multiplexer to select the suitable output.

Due to MUX at the end of critical path(switching activity high),the power
consumption and area of the adder independent structure is much higher than the
complex structure.
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Adder independent str. Has shorter path than complex
str. Thus adder independent str. Is faster.


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COMPARING ADDER INDEPENDENT STR AND
CHAIN STR.
Power consumption of logic operation block is not significant here.








To investigate which structure is more power effective, three groups of
test benches that generate at random are choosen.

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The result is shown in table III and fig.10

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Table IV shows that the adopting operand isolation technology, the
power consumption of adder independent str. And chain structure
declined.
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8-bit ALU that performs 10 different basic operation with three different
architecture were designed.

Complex structure has smallest area and is most power effective.

Using complex structure instead of other two structure ,min power
saved is 19.38% and max area saved is 56.37%.

Low power design can be implemented at all levels of design flow.

The work we do here gives some advice on selecting different
architecture when designing a low power ALU.
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[1] Swaroop Ghosh and Kaushik Roy, "Exploring High-Speed Low
Power Hybrid Arithmetic Units at Scaled Supply and Adaptive
Clock-Stretching", 2008 Asia and South Pacific Design Automation
Conference, p635, 2008.

[2] International Conference on Mechanical & Electrical
Technology(ICMET 2010)

[3] wikipedia

[4] Patanjali Prakash and Saxena A.K, Design of low power high
speed ALU using feedback switching logical, 2009 International
Conference on Advances in Recent Technologies in
Communication and Computing, p899-902, 2009.

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THANK YOU
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