CMOS CURRENT-MODE MULTIPLIER/DIVIDER

CONTENT
INTRODUCTION PRINCIPLE OF OPERATION CIRCUIT IMPLEMENTATION MATHEMATICAL REPRESENTATION MEASUREMENT RESULT CONCLUSION REFERENCES

INTRODUCTION
Current mode analog multiplier/divider circuit is suitable for standard CMOS fabrication and can be successfully applied to a wide range of different analog systems. Its main features are simplicity, low-voltage operation, low power consumption, an area efficient implementation. In addition, it is insensitive to temperature and process variation.

PRINCIPLE OF OPERATION
The approach followed to implement the current-mode multiplier/divider will be the combination of a geometric mean circuit and a squarer/divider circuit . Consider the following expression: Iz =
IxIy Iw

(1)

Ix, Iy, Iw and Iz being current signals

Equation (1) can be equivalently written as:

CIRCUIT IMPLEMENTATION
Below figure is the implementation of the idea of figure 1.

 Transistor always operate in saturation, which is enforced by properly choosing the bias voltage It is a based on forcing transition from triode region to saturation region and vice versa in transistor

MATHEMATICAL REPRESENTATION
To describe the basic operation of the circuit, following expression is employed for the drain current of a MOS transistor.

 It is assumed that the threshold voltage of all NMOS transistor is same, and that transistor are matched, having the same transconductance factor Transistors are also matched, and their aspect ratio is times larger than the aspect ratio of transistor being an integer greater than 1. Hence their transconductance factor is

 Consider the half circuit in the left hand side the voltage in transistor is,from (6):

MEASUREMENT RESULT
Considering the following values for nMOS &pmos as, threshold voltage 0.67V,-0.96 resp. aspect ratio( ) are 20/2 160/1 60/2 and 200/1 Hence, the n factor in the equations above is 4.The supply voltage employed is 1.5V, and is 1.3V, is 0.2V. The measured dc transfer characteristics are shown below. For this taking = .

 And sweep steps.

from

from

 Now for divider, the characteristics obtain is shown below

CONCLUSION
A compact and versatile CMOS multiplier/divider circuit has been presented. It has a wide range of applications in analog circuits. Measurement result for CMOS test chip shows accuracy, suitability for low-voltage operation, and low power consumption.

REFERENCES
[1] A.J.Lopez-Martin and Carlos A. De La Cruz Blas Low voltage CMOS current-mode multiplier/divider in proc. Of IEEE pp 1583- 1586, in 2010. [2] A.J. Lopez-Martin and A. Carlosena, A systematic approach to the synthesis of square-root domain systems, in Proc. of IEEE Int. Symp. on Circuits and Systems, Orlando, FL, 1999, vol. V, pp. 306-309. [3] J. Ramirez-Angulo Highly linear four quadrant BiCMOS analogue multiplier for 1.5V supply operation, Electron. Lett., vol. 28, no. 19, pp. 1783-1784, 1992. [4] S. I. Liu, Low voltage CMOS four-quadrant multiplier. Electron. Lett., vol. 30, no. 25, pp. 2125-2126, Dec.1994.