Yr09 Lecture05 Coughlan

Introduction to Programmable Logic Devices
John Coughlan STFC Technology Department Detector & Electronics Division
PPD Lectures
Programmable Logic is a Key Underlying Technology for PP Experiments.
First-Level and High-Level Triggering

Data Transport (Networks) Computers interacting with Hardware (Networks) Silicon Trackers (Millions of Data Channels)
Commercial Devices. Developments driven by Industry. Telecomms, Gaming, Aerospace, Automotive, Set-top boxes.
john.coughlan@stfc.ac.uk
The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
CMS CERN LHC Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power
CMS CERN LHC Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power
Electronics Rooms Trigger Systems. DAQ Systems. DIGITAL

Custom Digital Processing Boards VME Bus Crates The Design Warriors Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com)
Special Dedicated Logic Functions (not possible in CPUs)

Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate Timing Massively Parallel Data Processing (Silicon Trackers with Millions of Channels)
Custom Designed Printed Circuit Boards PCBs.
Commercial Programmable Logic Devices, FPGAs
CMS DAQ/Trigger Architectures
CMS
Fully custom PP ASICs
Programmable Logic DIGITAL
CPUs Commodity PCs
Telecoms Network ~ 1 Tbps
Lecture Outline
Programmable Logic Devices

Basics Evolution
FPGA Field Programmable Gate Array
Architecture
Design Flow

Hardware Description Languages Design Tools
Digital Logic
Logic Gates
Digital Logic
Logic Gates
Transistor Switches
Digital Logic
Logic Gates
MOORES LAW
Transistor Switches
< 40 nm ! $$$
Digital Logic
Digital Logic Function
Product AND (&) Sum OR (|)
3 Inputs
Black Box
Truth Table (Look Up Table LUT)
SUM of PRODUCTS
Digital Logic
3 Inputs
Black Box
SUM of PRODUCTS
Digital Logic
3 Inputs
Black Box
SUM of PRODUCTS
Programmable Logic Devices PLDs

Inputs ANDs Un-programmed State
SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC
Planes of ANDs, ORs ORs Outputs Logic Functions



Sums
Programmed PLD Product Terms

Logic Functions
Programmed PLD
Sums
Product Terms

Logic Functions
x x
x
Programmed PLD
x
Sums
Product Terms

Logic Functions
GLUE LOGIC
x x
x x
x
Programmed PLD
x
Sums
Product Terms
Complex PLDs
CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links
Feedback Outputs
CPLD Architecture
Sequential Circuits
Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)
Inputs
Sequential Circuits
Intermediate Inputs
New Output every clock edge
CLOCK
Register
EDGES
Sequential Circuits
Intermediate Inputs
New Output every clock edge
Clock Rate determines speed CLOCK

Register
Comb Logic Must meet Timing => Predictable circuits

Shift Registers, Pipelines, Finite State Machines
EDGES
Field Programmable Gate Arrays FPGA
Field Programmable Gate Array
Simple Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for memory chips (Moores Law)
Field Programmable Gate Array
Simple Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moores Law)
Huge Density of Logic Block Islands 1,000 100,000s in a Sea of Interconnects
FPGA Architecture
Logic Blocks

Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs)
16-bit SR 16x1 RAM
a b c d e clock clock enable set/reset
4-input LUT
y mux flip-flop q
FPGA Fabric
Logic Block
Look Up Tables LUTs

LUT contains Memory Cells to implement small logic functions Each cell holds 0 or 1 . Programmed with outputs of Truth Table Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR 16x1 RAM
3 6 Inputs
a b c d e
4-input LUT
y mux flip-flop q
clock clock enable set/reset

SRAM
SRAM
Multiplexer MUX
Static Random Access Memory SRAM cells

Look Up Tables LUTs

LUT contains Memory Cells to implement small logic functions Each cell holds 0 or 1 . Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells
3 Inputs LUT -> 8 Memory Cells
16-bit SR 16x1 RAM
3 6 Inputs
a b c d e
4-input LUT
y mux flip-flop q
clock clock enable set/reset

SRAM
SRAM
Multiplexer MUX
Static Random Access Memory SRAM cells

Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together
Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together Determined by SRAM cells
SRAM
SRAM cells
Clocked Logic

Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency)
16-bit SR 16x1 RAM
a b c d e clock clock enable set/reset
4-input LUT
y mux flip-flop q
FPGA Fabric Special Routing for Clocks Clock from Outside world (eg LHC bunch frequency)
Input Output I/O Getting data in and out

1 0
General-purpose I/O Up to > 1,000 I/O pins (several 100 MHz) banks 0 through 7
3 6
Input Output I/O Getting data in and out

1 0
General-purpose I/O Up to > 1,000 I/O pins (several 100 MHz) banks 0 through 7
3 6
Special I/O SERIALISERS ~ 10 Gbps transfer rates
Transceiver block Differential pairs
FPGA
Optical TRx
Designing Logic with FPGAs

Design Capture. High level Description of Logic Design.
Graphical descriptions Hardware Description Language (Textual)

Graphical State Diagram Textual HDL
When clock rises If (s == 0) then y = (a & b) | c; else y = c & !(d ^ e);
Top-level block-level schematic
Graphical Flowchart
Block-level schematic
Hardware Description Languages

Language describing hardware (Engineers call it FIRMWARE) Doesnt behave like normal programming language C/C++ Describe Logic as collection of Processes operating in Parallel Language Constructs for Synchronous Logic Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic Not all constructs can be implemented in FPGA! 2 Popular languages are VHDL , VERILOG Easy to start learning Hard to master!
VHDL
ENTITY Declaration Input Output to Module (STD LOGIC)
SIGNALS Declaration WIRES
CONCURRENT ASSIGNMENTS
CONDITIONAL ASSIGNMENTS => MULTIPLEXERS
VHDL
PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
COMPONENT Declaration
High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device

Mapping Routing
Schematic capture
Gate-level netlist
BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR; GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q); END CIRCUIT=TEST;
Bit File for FPGA Commercial CAE Tools (Complex & Expensive) Logic Simulation
Design Flow
Mapping Packing Place-andRoute
Timing analysis and timing report Gate-level netlist for simulation SDF (timing info) for simulation
Fully-routed physical (CLB-level) netlist

Mapping Routing
Schematic capture
Gate-level netlist
Design Flow

Mapping Routing
Schematic capture
Gate-level netlist
Design Flow
Configuring an FPGA

Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs
JTAG Port
Configuration data in Configuration data out
= I/O pin/pad = SRAM cell
SRAM
Configuring an FPGA

Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs
JTAG Port
Configuration data in Configuration data out
= I/O pin/pad
Programming Bit File
= SRAM cell
SRAM
JTAG Testing

Large Complex Functions Re-Programmability, Flexibility. Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor Fast Turnaround Designs Standard IC Manufacturing Processes. Moores Law Mass produced. Inexpensive. Many variants. Sizes. Features. PP Not Radiation Hard Power Hungry No Analogue
FPGA Trends

Number of LCs
State of Art is 40nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA)
1.00E+09 1.00E+08 1.00E+07 1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 1985
Logic Block cost ~ 1$ in 1990 Today < 0.1 cent
1990
1995
2000
2005 Year
2010
2015
2020
2025
0.1
$ / LC
Problems
0.01
Power. Leakage currents. Design Gap
0.001
CAE Tools
0.0001 1990 1995 2000 2005 2010 2015
Summary
Programmable Logic Devices

Basics Evolution
FPGA Field Programmable Gate Arrays
Architecture
Design Flow

Hardware Description Languages Design Tools
Importance for Particle Physics Experiments

References
The Design Warriors Guide to FPGAs
Clive Maxfield, Newnes Elsevier
VHDL for Logic Synthesis
Andrew Rushden, Wiley
FPGA manufacturer web sites

www.xilinx.com www.altera.com
FPGA Online

www.pldesignline.com www.fpgajournal.com www.doulos.com
Spare Slides
System on a Chip
Add Embedded Micro-Processor Cores in Fabric

e.g. RISC PowerPC Ethernet Interface
Run Operating System e.g. Linux
Combine Micro-Processor & Massively Parallel Logic

uP uP
Dual Design Flows

uP
Firmware HDL Software C

(a) One embedded core
uP
uP
(b) Four embedded cores
Time line of Programmable devices
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs FPGAs
Application Specific Integrated Circuits ASICs

PLDs ASICs
Prefabricated Programmed
SPLDs CPLDs
The GAP
Gate Arrays Structured ASICs* Standard Cell Full Custom

*Not available circa early 1980s
Custom Fabricated Design from Scratch
Limited Complexity Thousands of Gates
Large Complex Functions . Millions of Gates Customised for Extremes of Speed, Low Power, Radiation Hardness (Very) Expensive to Design (in small quantities) > $1 Million mask set (Very) Hard to Design. Long Design cycles. NOT Reprogrammable. FROZEN in Silicon. High Risk
Cheap Easy to Design Reprogrammable.

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Introduction to Programmable Logic Devices

John Coughlan STFC Technology Department Detector & Electronics Division

First-Level and High-Level Triggering

Particle Physics Electronics

Particle Physics Electronics

Electronics Rooms Trigger Systems. DAQ Systems. DIGITAL

Particle Physics Electronics

Special Dedicated Logic Functions (not possible in CPUs)

Custom Designed Printed Circuit Boards PCBs.

Commercial Programmable Logic Devices, FPGAs

CMS DAQ/Trigger Architectures

Fully custom PP ASICs

Programmable Logic DIGITAL

CPUs Commodity PCs

Telecoms Network ~ 1 Tbps

Programmable Logic Devices

FPGA Field Programmable Gate Array

Hardware Description Languages Design Tools

Digital Logic Function

Product AND (&) Sum OR (|)

Truth Table (Look Up Table LUT)

Digital Logic Function

Product AND (&) Sum OR (|)

Truth Table (Look Up Table LUT)

Digital Logic Function

Product AND (&) Sum OR (|)

Truth Table (Look Up Table LUT)

Programmable Logic Devices PLDs

SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC

Planes of ANDs, ORs ORs Outputs Logic Functions

Programmable Logic Devices PLDs

SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC

Planes of ANDs, ORs ORs Outputs Logic Functions

Programmable Logic Devices PLDs

SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC

Planes of ANDs, ORs ORs Outputs Logic Functions

Programmable Logic Devices PLDs

SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC

Planes of ANDs, ORs ORs Outputs Logic Functions

Programmed PLD Product Terms

Programmable Logic Devices PLDs

Programmable Logic Devices PLDs

Programmable Logic Devices PLDs

New Output every clock edge

New Output every clock edge

Clock Rate determines speed CLOCK

Comb Logic Must meet Timing => Predictable circuits

Field Programmable Gate Arrays FPGA

Field Programmable Gate Array

Field Programmable Gate Arrays FPGA

Field Programmable Gate Array

Huge Density of Logic Block Islands 1,000 100,000s in a Sea of Interconnects

Field Programmable Gate Arrays FPGA

16-bit SR 16x1 RAM

a b c d e clock clock enable set/reset

Look Up Tables LUTs

clock clock enable set/reset

Static Random Access Memory SRAM cells

Look Up Tables LUTs

clock clock enable set/reset

Static Random Access Memory SRAM cells

Larger Logic Functions built up by connecting many Logic Blocks together

16-bit SR 16x1 RAM