VLSI TESTING

MEMORY BIST by:

Saeid Hashemi Mehrdad Falakparvaz

1) : WHAT IS BIST ?

BIST (Built-In Self-Test) : is a design technique in which parts of a circuit are used to test the circuit itself .
Hardcore : Parts of a circuit that must be operational to execute a self test

BIST categories :

Memory BIST Logic BIST Logic + Embedded memory (ASICs)

Applications : Mission-critical sytems, selfdiagnostic circuitry (consumer electronics).

2) : BIST Concepts

BIST Techniques Test Pattern Generation Techniques (TPG) Test Response Compression Techniques

3 ) BIST Techniques

The BIST techniques are classified bassed on the operational condition of the circuit under test (CUT):

Off-Line BIST On-Line BIST

3-1) : On-Line BIST

Testing occures during normal functional operating conditions (No test mode, Real-Time error detection). Concurrent :Occures simultaneously with normal functional operation (Realized by using coding techniques). Nonconcurrent : Carried out while in idle state (Interruptible in any state, realized by executing diagnostic software/firmware routines).

3-2) : Off-Line BIST

Deals with testing a system when it is not carrying out its normal functions (Test mode, Non-Real-Time error detection). Testing by using either on-board TPG + Output Response Analyzer (ORA) or Microdiagnostic routines. Structural : Execution based on the structure of the CUT(Explicit fault model - LFSR, ...). Functional : Running based on functional description of CUT(Functional fault model Diagnostic software).

4) : Test Pattern Generation Techniques

Exhaustive : Applying all 2**n input combinations, generated by binary counters or complete LFSR. Pseudoexhaustive : Circuit is segmented & each segment is tested exhaustively(Less no. of tests required):

Logical segmentation : Cone + Sensitized-path Physical segmentation

4 ) : Test Pattern Generation Techniques (Cont.)

Pseudorandom : Not all 2**n input

combinations, Random patterns generated deterministically & repeatably, pattern with/without replacement, applicable to both combinational and sequential circuits.

weighted : Non-uniform distribution of 0s & 1s, improved fault coverage, using LFSR added with combinational circuits. Adaptive : Using intermediate results of fault simulation to modify 0s & 1s weights, more efficient,more hard ware complexity.

5) : Test Response compression techniques

Response compression : A process to form a signature from complete output responses. Signature : Compressed form of saved test results. Alias : Errorous output when faulty & fault-free sig. are the same. Compression procedure : Composition of test vector applying, results storing and comparision of the faulty & faultfree signatures. Compression of : Simple hardware implementation. Small performance degradation - No effect on normal circuit behaviour (delay, execution time). High degree of compression - Signature lenghts to be a logarithmic factor of responses lenghts. Small aliasing errors.

5) : Test Response compression techniques

(cont.)

Compression problems :
Existing aliasing errors. Calculating the good circuit signature.

Calculation of good circuit signatures :

Golden Unit : Applying the test to good part of the CUT. Simulation : Simulating the CUT and making sure of having good signature. Fault Tolerant : Producing copies of CUT and conclude the correct signature by finding the subset which generates the same signature.

5) : Test Response compression techniques

(cont.)

Ones count : The no. of times when 1 occurs in each output (counter). Transition count : The no. of transitions(0 =>1,1=>0) in the output (XOR +counter). Parity checking : The parity of response string, 0 if even & 1 if odd (XOR + D-FF). Syndrome checking : the normalized no. of 1s inoutput string (k/2**n when k is no. of minterms in an n input circuit), (All possible combination tests). Signature analysis : Based on redundancy checking (LFSR).

6) : Factors affecting the choice of BIST

Degree of test parallelism Fault coverage Level of packaging Test time Complexity of replaceable unit Factory and field test-and-repair strategy Performance degradation Area overhead

6-1) : Advantages
Lower cost of test Better fault coverage Possibly shorter test times Tests can be performed throughout the operational life of the chip

6-2) : Disadvantages

Silicon area overhead Access time Requires the use of extra pins Correctness is not assured

7) : BIST key elements

Circuit under test (CUT) Test pattern generators (TPG) Output response analyzer (ORA) Distribution system for data transmission between TPG, CUT and ORA BIST controller

8) : Specimen BIST architecture

Chip, Board or System

TPG

D I S T

CUT

CUT

D I S T

ORA

BIST controller

9) : Memory BIST

Memory types
SRAM,DRAM,EEPROM,ROM

Fault models
SAF,TF,CF,NPSF,AF

Test algorithms Test categories

9-1) : Fault models

Stuck-At Fault (SAF)

The logic value of a cell or a line is always 0 or 1

Transition Fault (TF)

A cell or a line that fails to undergo a 0=>1 or a 1=>0 transition

Coupling Fault (CF)

A write operation to one cell changes the content of a second cell

9-1) : Fault models

cont.

Neighborhood Pattern Sensitive Fault (NPSF)

The content of a cell , or the ability to change its content , is influenced by the contents of some other cells in the memory

Address Decoder Fault (AF)

Any fault that affects address decoder
With a certain address , no cell will be accessed A certain cell is never accessed with a certain address ,multiple cells are accessed simultaneously A certain cell can be accessed by multiple addresses.

9-2) : Memory test algorithms

Traditional tests

zero-one,checkerboard,GALPAT,Walking 1/0,Sliding Diagonal,Butterfly

March tests : Tests for stuck-at ,transition and coupling faults

MATS ,Marching1/0 ,March X , ...

Tests for neighborhood pattern sensitive faults (NPSF)

9-3) : Memory test categories

DC : Tests to verify analog parameters

Open/short -Power consumption-leakage,threshold,... Signal rise/fall time, Setup/hold time, Delay, Access time, .

AC : Tests to verify timing parameters

Dynamic tests : Detects dynamic faults affecting CUT(Recovery, refresh line stuck-at, bit-line precharge voltage imbalance, )

10) : Advanced Topics

Built-In Self-Repair(BISR). Programmable memory BIST Generalized Linear Feedback Shift Registers(GLFSR) for pseudo random memory BIST Transparent BIST for RAMs. And ....