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By Thomas Kuehl Senior Applications Engineer Precision Analog Linear Applications Engineering
This is your IC
Presentation Subjects
ESD High voltage (kVs) Short duration event (1-100ns) Fast edges Low power Out of circuit event
EOS Low voltage >Vs Longer duration event Low power In-circuit event
ESD
PC Board
EOS
-5V bus
V1 5 L1 50n C1 100n R2 10k OP2 !OPAMP Vout + C2 100n R4 1k
0V
+ VG1 R3 1k L2 50n
+5V bus
V2 5
The TI data sheet Absolute Maximum Ratings is a good place to check and assure EOS problems are avoided
U1 OPA735 Vo
+
*
+
Input voltage
CMV input range 0V -0.1V -0.5V Safe with Rs -5.0V -100V ESD protect region -2kV Neg rail Neg safe
Vi 2.5
C1 100n
V1 5
R1 1.5k
L1 7.5u
VG1
ESD model Human Body Model Machine Model Charged Device Model HBM MM CDM
R 1.5 k 20 20
C1 100p
d (i) R * di 1 * i 0 2 L dt LC dt
L 7500 nH 750 nH 5 nH
IC1
DUT
R1 1.5k SW1 t C2 2p Rdut 10 VF1
2kV
IC L1 7.5u
C1 100p
1.5 1.0
AM1
Rdut = 10 Ohms
0.0 15.0 10.0 VF1 (Volts) 5.0 0.0 0 50n 100n Time (s) 150n 200n
Machine Model
Machine ESD Model modeled in TINA Spice
IC1
DUT
R1 10 SW1 t C2 2p Rdut 10 VF1
200V
IC L1 500n
C1 200p
4.0
Rdut = 10 Ohms
2.0 AM1 (Amps) 0.0 -2.0 40.0 20.0 VF1 (Volts) 0.0 -20.0 0 50n 100n Time (s) 150n 200n
AM1
200
Voltage (V)
0
VG1
250V
-200
C1 10p 2 - 10pF
Rdut 10
T 5.0
0.0
1.0n
3.0n
4.0n
Cp: 6p[F]
Cp 2p
2.5
AM1
Current (A)
0.0
-2.5
R4 19.5
Pad
V+
C1 20f
D2 1N914 D1 1N914
Pad/Pin
R2 74 R1 190
Input Pad
Pad
C1 20f V-
SCR
C1 20f V-
Rb
Vee
R4 10.2
R4 9.4
R4 9.4
R4 9.4
R4 9.4
R4 9.4
R4 9.4
Absoption circuit
OR
input pad
NPN bipolar
on high-speed process
T1 !NPN RB 500 V-
NMOS Clamp
V+ V+
T2 Noname RB 500 V-
V-
ON OFF
Drain (collector)
Gate
Source (emitter)
n
p
Sub (base)
P-sub/epi
Input protection
D1 1N4148
ultra low leakage diodes
V+
Output protection
D3 1N4148
Rs 1k In+
+ IOP1
D5 1N4148
Vo
D6 1N4148
D2 1N4148
Rs 1k
D4 1N4148
In-
T1 !NPN
Rb 2k
V-
Input pin
ESD2 N-sinker BL ESD1 NPN B-E
Supply clamp
V+ pin at GND
V+
D1 1N4148
D3 1N4148
D5 1N4148
In+
Rs 1k
Vout at GND
Vo T1 !NPN
+ IOP1
+
VG1
D2 1N4148
Rs 1k
D4 1N4148
D6 1N4148
In-
Rb 2k
V-
V- pin at GND
V-
U1 OPA364
VG1
TL1
+
Vo
+
VG2
V+
R3 10k
VG2 500.00m 0.00 3.25 Vin+ 500.00m -2.25 2.50 Vo 0.00 -2.50 0.00 5.00m 10.00m Time (s) 15.00m 20.00m
VG1
C1 100n
C2 100n
*
D1 1N4148 D3 1N4148
L4 10n
D5 1N4148
Intended signal
VG1
Rs 1k
+ IOP1
D6 1N4148
D2 1N4148
Rs 1k
D4 1N4148
T1 !NPN RL 10k Rb 2k
VG2
RF 10k
RI 1k
V1 5
* L1 50n
L3 10n C1 1u +
A supply clamp transistor failure during resulting from an input EOS/ESD event
R1 500
TL1
R4 75
V+
TI quad CMOS operational amplifier failing unexpectedly in air conditioner application TI FA report indicated the operational amplifier die had carbonized material on die and pin 4 (V+) to pin 11 (V-) short EOS analysis of the customer application input and output ESD circuits did not reveal any likely candidates
A request for the Field Applications Engineers to observe and monitor the amplifier pins during the various operational cycles was made and provided
They found that a 20 Vpk pulse was appearing on the V+ line during operation of the air conditioner. The nominal supply voltage was +5 V The EOS was causing either the supply-to-supply ESD clamp to break down, or voltage breakdown of the amplifier transistor structures A higher voltage operational amplifier and a transient voltage suppressor on the V+ line were recommended
VS1 5 Compliance Range +/-7.5V I max 150mA VCCS1 + Pin under test +
A
+ +
AM1 U1 OPA348
+ VG1 -
SW1 +
The continuous input overload current is set to < 1/10th the JEDEC maximum latch test current (t 10ms)
30.0m
AM115.0m 0.0 3.50 VG1 1.75 0.00 5.00 VG2 2.50 0.00 3.50 VM1 1.75 0.00 0 10m 20m Time (s) 30m 40m 50m
V+
Vin-
Ov er-Voltage Protection
RG 25k EXT
Vin+
Ov er-Voltage Protection
+ IOP2
Vbias 0 Vbias
V-
A1
A3 +in A3 -in
A2 + Mirror of A1circuit
IOP2
C1 6p R1 25k RG 25k
Vd/2 1
+ +
Vcm 0
Vd/2 1
Ov er-Voltage Protection
Ext
Possible occurrences
T 10
U1 OPA227
-
V-
90%
Vo
+
8 VG1
Voltage (V)
VG1
R2 1k
V+
R3 1k
V1 15 V+ C1 100n
V2 15 VC2 100n
2
Vo
10%
0 0.0 1.0u 2.0u Time (s) 3.0u 4.0u 5.0u
Iin
20mA max
T28 !NPN
T41 !NPN
Vo
VinRL 1k
T44 !NPN
VG1
Back-to-back clamp diodes are inherent and internal to the chopper switch structures
When Vin exceeds a Vcm maximum Vo is forced to an output rail level The op-amp is forced outside of its linear operating range The feedback loop collapses and an input differential voltage develops One clamp diode or the other becomes forward biased and the input bias current can increase tremendously This may limit the use of this type of operational amplifier as a comparator
Overload Recovery
Auto-zero CMOS Operational-amplifiers
OPA335 Av = -50V/V
R1 2k R2 100k
VG1
U1 OPA335 V+
+ V1 2.5
VM1
V2 2.5 C2 100n V-
Vin Vs / Gain
U1 OPA234
+4.5V
Vin 5Vp-p + 2.0Vdc
-
VG1
+ +
+ VM1 -
VG1 R1 50 V1 5 C1 10n
Output inversion
L1 100u
Rs 5
LOAD
C1 1u RL 1k
VG1
+ -
VM1
5V Power supply
10.0
Smoothing a transient
with an RLC filter Transient amplitude effectively reduced Ringing dependent on RLC values and load R Amplifier PSRR becomes important
VG1 7.5
VG1
5.0 5.5
VM1
VM1 5.0
Rs 10
LOAD
C1 10n RL 1k
VG1
+ -
VM1
10.0
Transient voltage suppression (TVS) diode 6.8V- 550V reverse standoff voltage Unidirectional & bidirectional models
VG1
VG1 7.5
5.0 7.0
VM1
VM1 5.8
Features Multilayer ceramic construction Operating voltage range VM(DC) = 5.5 to 120V Non-repetitive surge current (8/ 20us) Non-repetitive energy (10/ 1000us) response time <1ns for zinc oxide Inherent bidirectional clamping Wider temperature range and flatter response than solid-state TVS
V1 5 C1 100n
+ R2 5k -
VM1
Features: Forward voltage Forward current Leakage current * Diode capacitance VF 380mV, IF = 1mA IF = 200mA max (cont.) IR 100nA, VR = 30V Ctot 5pF, VR = 0V
* A small-signal silicon diode (IN4148) will likely turn on at lower voltage than the internal ESD silicon diode and may exhibit lower leakage current than a Schottky diode.
Protection components such as transient voltage suppressors (TVS), diodes and zener diodes all exhibit capacitance even when biased off The capacitance will vary to some extent with the voltage applied across the protection device Most often the capacitance does not have a linear capacitance to voltage relationship (voltage coefficient) This non-linear capacitance to voltage relationship may increase distortion in the protected circuit It will be most evident in a very low THD circuits, but may not degrade performance significantly
The internal output ESD cell is unlikely to withstand the open-circuit HV pulse - latching is probable
In Summary
EOS and ESD events may activate ESD protection but result in different outcomes Internal ESD circuits may sufficiently handle EOS Be aware of unique EOS situations such as power up and input slewing External EOS protection circuits will be required if device damage is likely to occur without it