Impact of Interconnect Parasitics

Reduce Robustness

Affect Performance
Increase delay Increase power dissipation

Classes of Parasitics Capacitive

Resistive
Inductive

INTERCONNECT

Capacitive Cross Talk

X

CXY
VX CY Y

Capacitive Cross Talk Dynamic Node

V DD
CLK

CXY

In 1 In 2 In 3

CY

PDN

X
2.5 V

0V

CLK

3 x 1 mm overlap: 0.19 V disturbance

Capacitive Cross Talk Driven Node

0.5 0.45 0.4 X VX 0.35

RY

CXY Y

tr
tXY = RY(CXY+CY) V (Volt)

0.3
0.25 0.2 0.15

CY

0.1
0.05 0 0 0.2 0.4 0.6 0.8 1

t (nsec)

Keep time-constant smaller than rise time

Dealing with Capacitive Cross Talk

Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as possible Differential signaling Do not run wires together for a long distance Use shielding wires Use shielding layers

Shielding
Shielding wire
GND

V DD

Shielding layer

GND

Substrate (GND )

Cross Talk and Performance

- When neighboring lines switch in opposite direction of victim line, delay increases
Cc

DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES

Miller Effect
- Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV)

Impact of Cross Talk on Delay

r is ratio between capacitance to GND and to neighbor

Structured Predictable Interconnect V S G S V S

S V

Example: Dense Wire Fabric ([Sunil Kathri])

Trade-off: Cross-coupling capacitance 40x lower, 2% delay variation Increase in area and overall capacitance Also: FPGAs, VPGAs

 Both delay and power are reduced by dropping interconnect capacitance Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k) The numbers below are on the conservative side of the NRTS roadmap

Interconnect Projections Low-k dielectrics

Generation Dielectric Constant

0.25 mm 3.3

0.18 mm 2.7

0.13 mm 2.3

0.1 mm 2.0

0.07 mm 1.8

0.05 mm 1.5

Encoding Data Avoids Worst-Case Conditions

In Encoder

Bus

Decoder
Out

Driving Large Capacitances

V DD

V in

V out
CL

Transistor Sizing

Cascaded Buffers

Using Cascaded Buffers

In
1 2 N

Out
CL = 20 pF

0.25 mm process Cin = 2.5 fF tp0 = 30 ps

F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns

(See Chapter 5)

Output Driver Design

Trade off Performance for Area and Energy Given tpmax find N and f Area f 1 F 1 A 1 f f ... f A A A f 1 f 1
2 N 1 N driver m in m in m in

Energy

Edriver 1 f f 2 ... f

N 1

C V
i

2 DD

F 1 C 2 2 CiVDD L VDD f 1 f 1