Basic I/O Interfacing

Objectives
Operation of basic I/O operations Decode 8-, 16, and 32-bit addresses for enabling I/O ports Handshaking for I/O operations Interface and program the 82C55 PPI (programmable peripheral interface) Using the 82C55 to connect LEDs, keyboards, etc. to the processor Interface stepper and DC motors to the processor Interface and program the 16550 programmable asynchronous serial interface adapter (UART) Interface and program the 8254 programmable interval timer (PIT)

I/O Instructions
Two types: - Transfer data between the processor accumulator (AL, AX, EAX) register
and I/O device: IN and OUT - Transfer string data between memory and I/O device directly: INS and OUTS (for processors above 8086) The IN instruction (I/O Read): Inputs data from an external I/O device to the accumulator. The OUT instruction (I/O Write): Copies the contents of the accumulator out to an external I/O device. The accumulator is: - AL (for 8-bit I/O), - AX (for 16-bit I/O), - EAX (for 32-bit I/O).

I/O Address
As with memory, I/O devices have I/O addresses (addresses for the I/O port) Up to 64K I/O bytes can be addressed The 16-bit port address appears on address bus bits A15-A0 This allows I/O devices at addresses 0000H-FFFFH Two ways to specify an I/O port address: - An 8-bit immediate (fixed) address (specified as a byte in the instruction): e.g. IN AX, p8 ; Reads a word from port p8 0000H-00FFH (can only see the first 256 addresses) - A 16-bit address located in register DX (can be easily varied): e.g. OUT DX, AL; outputs the byte in AL to the port whose address is in DX 0000H-FFFFH (upto 16K addresses). i.e. high port addresses are accessible only through DX addressing
DX
00FF

Immediate 4

I/O Data widths

As with memory, I/O ports are also organized as bytes A port can be 1, 2, or 4 bytes wide (not 8 bytes wide on the Pentium)
Low Endian scheme: Low address byte contains low end (LS) part of data

00F3H 00F2H

Port is 4 bytes wide

EAX Port is 2 bytes wide 00F1H

AX

Port is 1 byte wide

5

Port Address p8

00F0H

LS byte

AL

INS and OUTS I/O instructions

They address I/O port using register DX Transfer string data between port and memory - INS: Moves string data to the Extra Segment; ES:DI - OUTS: Moves data from the Data Segment; DS:SI As with other string instructions, flag) bit Data width of transfer specified by using INSB, INSW, and INSD for byte, DI and SI can be automatically

incremented or decremented depending on the state of the DF (direction

word, and double word

Can be prefixed with REP to repeat the instruction for a number of times stored in CX
6

(Note corrections)

Width of Transfer Determined by the A register used Width of Transfer Determined by the Instruction used
No argument, DX by default

DX DX DX

Isolated vs. Memory Mapped

I/O can be either: - Isolated, or - Memory mapped Isolated I/O: uses the dedicated I/O instructions (IN, OUT and INS, OUTS) and has its own address space for I/O ports (0000H-FFFFH)- isolated from the memory address space Memory mapped I/O: uses memory reference instructions , e.g. MOV, and a region of the memory address map. So address space is shared between memory and I/O (used by only one of them) Both techniques can be used with Intel processors

But most Intel-based systems e.g. the PC, use isolated I/O
Some other processors do not have dedicated I/O instructions and therefore use only memory-mapped I/O addressing, e.g. the PowerPC microprocessor (Macintosh computers)
8

Memory and I/O address Maps for the 8086/8088 Memory: MOV a. Isolated I/O Using dedicated I/O instructions e.g. IN, OUT I/O: IN
00FF

I/O Port specified in DX, either explicitly or implicitly

64 K I/O bytes

Port specified immediately as a byte in the I/O instruction

MOV Range of memory addresses assigned for I/O transfers

b. Memory-mapped I/O Using ordinary memory transfer instructions e.g. MOV

Memory

The PC I/O space

The PC I/O space mainly exists at locations below I/O port 0400H

Main board devices appear at addresses 0000H through 00FFH

Early ancillary I/O devices appear at I/O locations 0100H through 03FFH

Modern components appear at I/O locations above 0400H

The slide on the next page shows many of the I/O devices found in the personal computer

10

The PC I/O Address Space

Processor communicates with and controls these peripherals through writing into/reading from their control registers accessed as I/O locations 03FF

Must use 16-bit variable I/O address in register DX

Reserved for use by system components and ISA bus

On Board Devices

0100 00FF
Interval (8254)

Can Use either: - Fixed (immediate) 8-bit I/O address in instruction, p8 - Variable 16-bit I/O address in register DX

0000

0000

11

IN (I/O Read)
The IN instruction primarily takes he following forms: Data from the Input port addressed
is put on the data bus for the processor to read into the A register

IN IN IN IN IN IN

AL,23H AL,DX AX,44H AX,DX EAX,2AH EAX,DX

;immediate ;DX holds address

Size of data transferred in each case?

12

OUT (I/O Write)

The OUT instruction primarily takes the following forms: Data from the A register is put on the data bus for
latching into the Output port addressed

OUT OUT OUT OUT OUT OUT

23H,AL DX,AL 4CH,AX DX,AX 1EH,EAX DX,EAX

;immediate ;DX holds port

Size of data transferred in each case?

13

In embedded systems, most I/O is 8-bits

To write the data 00H into Output port 62H MOV AL,00H OUT 62H,AL or MOV AL,00H MOV DX,62H OUT DX,AL To read a byte from Input port address 71H: IN AL,71H or MOV DX,71H IN AL,DX
14

Basic Input Port (for I/O Reads)

The basic input port connects an external set of bits to the mP data bus whenever the mP executes the correct IN instruction with the correct I/O port address External device puts data on the mP data bus Must include a 3-state (Tri-State) buffer to limit access to the processor data bus to the duration of executing the I/O instruction only

15

Basic 8-bit Input Interface: Reads the status of 8 toggle Switches (a byte read) Pull-up Resistors
Gate

To mP

0 1 Toggle switches
3-state buffer

The SEL signal is generated (active low) By decoding: - The address for the I/O port - The I/O READ operation

Outputs: Normally Hi-Z Unless device is Selected (both G1 and G2 low)

Circuit can be expanded for 16-bit (word) or 32-bit (DWord) interfaces 16

Basic Output Port (for I/O Writes)

The basic output port writes data from the mP data bus to an output port

whenever the mP executes the correct OUT instruction with the correct
I/O port address Must latch the processor data put on the bus during the I/O instruction to

make it available indefinitely for the port

No need for 3-state (Tri-State) buffers as the data bus is at the input side of the latch

17

Basic 8-bit Output Interface: Controls 8 LEDs (1: OFF, 0: ON)

Circuit can be expanded for 16-bit (word) or 32-bit (DWord) interfaces

From mP
Edge-triggered latch

No HiZ. O/P always enabled

OE

Data is latched and remains here until the next OUT instruction to this port is executed The SEL is generated (for + ive edge triggering) by decoding: - The address for the I/O port - The I/O WRITE operation 18

Parallel Port
The parallel port is an example of interfacing slow devices, e.g. a
printer, to the processor A printer can print say 100s of characters per sec (CPS), but the

processor can output as many as 1000s of CPS

To achieve flow control and proper operation we use a technique called handshaking

Handshaking regulates the flow of data from the processor to a slower

peripheral device to ensure correct operation

19

Interfacing
When connecting external input and output devices to the processor, we

must take into account the DC characteristics and drive capabilities of the
mP pins.

(Fan-out considerations For outputs before)

Input Devices, e.g. Switches mP

Output Devices, e.g. LEDs

mP Input

mP Output

Source Sink

Sink Source

20

Input Devices: The Switch

=5V

The most basic input device

Switches are passive- do not produce a

voltage, easily present a logic 0 to an I/P by grounding it. To make a switch TTL compatible, a pullup resistor is used as shown. The value should be between 1K and 27K W. Why not, say, 400 K W?
I in, High
(Single Pole Single Throw)

TTL Input to mP

The pullup resistor does the conditioning required to allow the switch to produce a TTL compatible input to the processor

Switches

bounce

and

this

is

often

undesirable.

Here, processor senses the switch effect directly- hence bouncing is a problem, especially if input Is used as a clock
Initial Posn

Wrong switch State Can Final Posn be read Here ! 21

The switch Bouncing Problem

Switch contacts bounce mechanically before it finally settles in the new position With the simple arrangement shown, bounces can lead to the wrong input being read by the processor The effect of switch bounces can be removed either: by Software: Simply wait a little before reading the new switch status by hardware Hardware solutions increase circuit cost and complexity

TTL Input to mP
22

Output Devices: The LED

LED diodes are used in many systems as indicators and as sources of infrared beams LED must be forward biased to conduct and emit light When conducting, a typical (Red, Green, or Yellow) LED 1.65 V _ 10 mA

passes a current of about 10 mA with a voltage drop

Vdiode 1.65 V (1.5 V - 2 V in practice)

A Blue, White, or Ultra Bright LED passes more current at a larger voltage drop, e.g. 30 mA @ 2.5 V.

A bit of electronics!
23

Interfacing the LED directly to a TTL O/P

10 mA currents can be easily sunk by a TTL output at the low state (0)
= +5V

=> (A standard 74 TTL O/P sinks up to 16 mA lower

values for lower power series e.g. 74LS sinks only 4 mA)

V diode + _
I min = 10 mA

Vout, low 0.1 V

Vdiode 1.65 V
To ensure I = 10 mA, R should be

Vout
LED ON indicates 1 or 0 at Input?

Vcc Vdiode Vout 10mA 5 1.65 0.1 0.325 KW 330 W 10

Nearest standard resistor value

24

Interfacing the LED through a transistor

If diode takes current > TTL sink current at the low state: Use a transistor to connect the LED Transistor current gain (b= Ic/Ib 100) reduces current requirement from the TTL circuit (e.g. the mP or the buffer IC) => Ib = Ic/100 = 10mA/100 0.1 mA => Rc calculated as before, similar value
Common Emitter

+ 1.65 V _
Ic = 10 mA Ib = 0.1 mA b c e Rb 0.7V 0.1V (Transistor Is saturated)

(TTL)

=> Rb should not be larger than:

Transistor: b = Base Use minimum gain value specified e = Emitter (worst case condition) c = Collector Vout, high, min 0.7 Rb Nearest standard 0.1mA resistor value 2.4 0.7 17 KW 18 kW 25 0.1

Driving larger currents and voltages; e.g. DC motors, mechanical relays, etc.
Large current loads such as motors or large relays require a Darlington pair in place of the transistor driver Two transistor gains in cascade, (b = b1 b2), so smaller base currents from TTL for large load currents Can use 12 V or higher supply Select a transistor that meets both the voltage and current requirements for the load The diode is used to prevent the transistor from being destroyed by the inductive kickback current that appears when the field collapses suddenly in the coil

12 V DC Motor
Vout, high, min 0.7 0.7 Rb 0.143mA (TTL) 0.7V 2 .4 1 .4 0.7V 7 KW 6.8 kW 1A/(7000)=0.143 mA 0.143

Ic = 1 A

Rb

b b1 b2

Diode off In normal operation

Current can not change instantly through an inductor. If it suddenly drops from I1 to 0, a negative current - I1 is generated which gradually decays to 0. The diode provides a safe path for this current away from the transistor

26

WK 9

Port Address Decoders

As with memory addresses, port addresses must also be decoded to select an I/O device for a particular port number. Memory mapped I/O is identical to memory access (with IO/#M = 0) Will consider here only isolated I/O (using dedicated instructions: IN, OUT, etc.)

Most embedded systems use only fixed I/O addressing:

- i.e. Only the least significant eight address bits A7-A0 are decoded. Limits number of I/O ports to 256 (enough)

PC systems used fixed/variable I/O addressing:

- All 16-bits of the I/O address A15-A0 are decoded, allowing the use of up to 64K ports Decoding is simpler than for memory- smaller # of address lines Isolated I/O transfers are activated using (depending on processor and mode): - IO/#M = 1, M/#IO = 0, #IORC, #IOWC, #RD, #WR, W/#R
27

Address Decoding for 8 I/O Ports: F0 to F7 for the 8088 using 8-bit I/O address
a. Using a Decoder IC
X X X X X X 0 1 1 0
MS part (Enable decoder)

Decoder I/Ps

Decoder O/Ps

LS part (Select port on decoder)

To Enable Inputs on the 8 I/O ports A7 ....A0 11110 000 = F0 1st 11110 001 = F1 2nd . 11110 111 = F7 7th
28

1 1 1 1 1 1

3-to-8 Decoder

Address from mP
Note: #IO/M decoding should be added

The 82C55 PPI

PPI = Programmable Peripheral Interface
The 8255 allows the microprocessor to communicate with the outside world

through three programmable 8-bit wide I/O ports

The PC uses a few 82C55 (in the chip set) to control the keyboard, speaker, and parallel port

The 8255 PPI is available in DIP or surface mount forms

Also implemented as functions within modern interface chip sets

29

Similar to a 4-byte RAM

3 programmable 8-bit I/O ports: A, B, C 2 Groups 12-bit groups A, B

Data Bus
2-bit Address I/P (select port or Command register for Read or Write)
Read/Write Control

Port A + Upper half of C = Group A (12 bits)

B
Port B + lower half of C = Group B (12 bits)

On the PC: Two 82C55s CS Input -One 82C55 occupies (low) 4 I/O ports 60H-63H: Handling Keyboard, timer, speaker, etc. -One 82C55 occupies 4 I/O ports 378H-37BH Parallel printer port

RESET initializes the PPI to operate in mode 0 & all 3 ports as inputs at power up. With all ports as input ports, this avoids damage to the device at Power up 30

82C55 DIP Version

31

I/O Port Assignments

Group A is Port A and upper of

A1

A0 Function

Port C (PC7-PC4).
Group B is Port B and lower of Port C (PC3-PC0).

0 0 1

0 1 0 1

Port A Port B Port C Command Register

32

Writing into this register programs the various ports to operate in various modes and be used as either inputs or outputs

Address from microprocessor

A1 A0 Inputs on 82C55 A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 0 0 0 0 0 = C0H Port A 1 1 0 0 0 0 1 0 = C2H Port B 1 1 0 0 0 1 0 0 = C4H Port C 1 1 0 0 0 1 1 0 = C6H Comnd Register
80386SX Processor

1 0 0 1 0 0 Address from 80386SX microprocessor

001

Select PPI At decoded mP address

33

Programming the 82C55

Using one internal register If bit 7 = 1 select format for Command Byte A If bit 7 = 0 select format for Command Byte B Bit 7 = 1: Command Byte A: Programs Groups A and B (as defined in terms of ports A, B, C - previous slide): - as either inputs or outputs - in either modes 0, 1, or 2

Program

Only for mode 0

Program

Bit 7 = 0: Command Byte B: Sets (to 1) or Clears (to 0) the specified one of 8 bits of port C (in modes 1 and 2)

34

8255 Modes
Mode 0 (for groups A & B)- the most commonly used mode: All 12 bits of the group
are simple inputs or simple latched outputs
Data Data

Mode 1 (for groups A & B)- is used occasionally to provide handshaking to an I/O device and operate asynchronously with the device. Most Port C bits are dedicated for handshake functions for the operation. A few are controlled separately using the Command byte B format for handshaking I/O.
Data

Control, e.g. Busy, Strobe, etc.

Mode 2 (for group A only- Group B not used)- is a bidirectional mode for Port A only

(Port B is not used). Port C provides handshaking signals.

35

8255 Modes

When O/P, Set or Reset Using Command Byte B

Not Used

Control: Handshaking For the data port

36

Programming the 82C55

To program the command register of the 82C55 and select operation use command byte A For example, to program all the ports as outputs and in mode 0 (the most common mode) use: MOV AL,80H MOV DX,COMMAND_PORT OUT DX,AL

= C6H address of command register

37

Mode 0 Application: 7-Segement Display

Segment Driver

Common 38

7-Segement Display
CA Vcc

Anode

Cathode

Select Segments: Switched Resistors to GND

CC
Select Segments: Switched Resistors to Vcc

GND

39

7-Segement Display

Anode

Cathode

Segment Data (1 byte) for each character

40

Multiplexed 7-Segement Display

Common Motivation for MUXing: To segment - Reduce the number of segment drivers on all Digits

by a factor of n

n=8 Digits

Sequentially Turn ON one digit at a time

Recommended rate: 100 1500 times per sec

41

Address decoding is similar to that of a 4-byte Read/Write memory

1 turns segment ON Tr 1 A: O/P Port: Segment data For selected digit Tr 2 Most Significant (MS) Digit

Multiplex the eight digit displays (only one is ON at a time)

0 turns digit B: O/P Port: digit ON B: O/P Port: Select # Displayed Select digit To be displayed

Vcc

GND PLD for 14-bit I/O address (A15-A2) + IO/#M decoding

Digit transistor switch Controlled by Port B bit, e.g. Tr 1 7 Segment data transistor switches 42 Controlled by Port A bits, e.g. Tr 2

1 digit . . . . . .

PLD Program for Address Decoding

library ieee; use ieee.std_logic_1164.all; entity DECODER_11_21 is port ( IOM, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_17 is begin D0 <= not IOM or A15 or A14 or A13 or A12 or A11 or not A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2; 82C55 end V1;
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 X X Total: 16-bit I/O address 14-bit address decoding Using PLD
On chip Selection

4 I/O ports: 0700 0701 0702 0703 Port A Port B Port C Control 43 Register

; Program the 82C55 for Port A and Port B are output ports in mode 0 MOV AL, 80H ; 80H Data into AL 8 bytes of MOV DX, 703H ; Address of Command Port into DX Digit Data OUT DX, AL ; Write 80H into Command Port In memory ; ; to program PPI MS Digit MEM+7 ; An assembly language procedure that multiplexes the 8-digit display. . ; This procedure must be called often enough for the display to appear stable . DISP PROC NEAR USES AX BX DX SI BX PUSHF . MEM LS Digit MOV BX,8 ;load counter BX with # of display digits MOV AH,7FH ;load initial digit selection pattern to enable MS digit (01111111) MOV SI,OFFSET MEM - 1 ;Load SI with offset (MEM) - 1 MOV DX,701H ;address Port B (for Port A: decrement DX) ;Sequentially display all 8 digits starting with MS digit .REPEAT MOV AL,AH OUT DX,AL ;send digit selection pattern to Port B DEC DX ;Address Port A (to send Digit Data) MOV AL,[BX+SI] ;Load digit data from memory into AL OUT DX,AL ;send digit data to Port A CALL DELAY ;wait 1.0 ms leaving displayed digit ON ROR AH,1 ;adjust selection pattern to point to next digit INC DX ;Address port B DEC BX ;decrement counter for data of next digit. .UNTIL BX == 0 Procedure for 1 ms delay, e.g. a loop of instructions POPF i.e. digit remains ON for 1 ms before moving to next RET 44 DISP ENDP

; Delay Loop DELAY D1: LOOP D1 RET ENDP PROC NEAR USES CX MOV CX, XXXX

; XXXX determines delay, = Delay required / loop exec time

DELAY

Loop execution time is calculated from instruction data and the clock frequency.
An 80486 executes LOOP D1 in 7 clock cycles With a 20 MHz clock, loop exec time = 7 x 50 = 350 ns XXXX = 1ms/350ns

Display Flashing Rate: - Assume the DISP Procedure is called continuously - Ignore loop execution times relative to delay time (e.g. 350 ns << 1 ms)
1 ms Digit Displayed 8 7 8 ms
DISP Proc DISP Proc

... 2 1 8 7

... 2 1

...

Flashing rate = 1/8 ms = 125 Hz 45

Applied Control Systems

Stepper Motors

46

Stepper Motor / Electro magnet

47

Rotor Stator Outside Casing

Coils

Stator
Rotor
1

N
2 2

S
1

Internal components of a Stepper Motor

48

Cross Section of a Stepper Motor

Stators

S N
2 2

S N
1

Rotor
49

Full Step Operation

Four Steps per revolution i.e. 90 deg. steps.

50

Half Step Operation

Eight steps per. revolution i.e. 45 deg. steps.

51

Winding number 1
1

N
6 pole rotor
2

N S

N
2

One step

S N S

Winding number 2
a b

52

Six pole rotor, two electro magnets.

How many steps are required for one complete revolution?

53

P P

54

55

STEP SEQUENCING There are three modes of operation which is determined by the step sequence applied. The three step sequences are: Wave Full

Half Stepping
HALF STEPPING: Combination

The half-step sequence has the most torque and is the most stable at higher speeds. It also has the highest resolution of the main stepping methods. It is a combination of full and wave stepping.

56

57

Stepper Motor Interface

Stepper motor is digital in nature It rotates in a sequence of discrete steps controlled by sequentially energizing a set of coils (windings) Step angles vary from 1 to 15 depending on precision required (and cost) C B
45 2 coils driven at a time 135

D
Anti-clockwise Rotation N Pole lies between the two energized coils Rotation Direction: Anti-clock wise Step angle: 90

ROL: Motor rotates anticlockwise

A B C D 0 0 1 1
ROR reverses the direction of Motor rotation

225

315

58

1 activates coil

Darlington pairs for driving high load currents

Anti-surge diodes

ROL

03H = 06H = 0CH = 09H =

Rotate instruction operates on whole byte 0011 We want to rotate half the byte duplicate pattern! 0110 ROL ROR 1100 Current angular 1001 POS 03H or 06H or 0CH or 09H Position stored at location Anti-Clockwise Clockwise POS (in memory) 59

60

Practical Stepper motor operation

The top electromagnet (1) is turned on, attracting the nearest teeth of a gearshaped iron rotor. With the teeth aligned to electromagnet 1, they will be slightly offset from electromagnet 2

The top electromagnet (1) is turned off, and the right electromagnet (2) is energized, pulling the nearest teeth slightly to the right. This results in a rotation of 3.6 in this example.

61

The bottom electromagnet (3) is energized; another 3.6 rotation occurs.

The left electromagnet (4) is enabled, rotating again by 3.6. When the top electromagnet (1) is again enabled, the teeth in the sprocket will have rotated by one tooth position; since there are 25 teeth, it will take 100 steps to make a full rotation in this example. 62

Stepper motor applications

Stepping Motor to move read-write head

63

Stepper motor applications

Paper feeder on printers

Stepper motors

CNC lathes

64

Stator coils

Rotor

CNC Stepping Motor

65

Advantages / Disadvantages
Advantages:-

Low cost for control achieved

Ruggedness Simplicity of construction Can operate in an open loop control system Low maintenance Less likely to stall or slip Will work in any environment Disadvantages:Require a dedicated control circuit

Use more current than D.C. motors

High torque output achieved at low speeds

66

67

8253/4-Programmable Interval Timer (PIT)

68

Necessity
It solves:
Generation of accurate time delays in microprocessor system under software control (No processing overhead due to looping to create a delay-the microprocessor can trigger the counting and do some other job while the timer is producing necessary delays)

69

8253 / 8254 Timer

PIT, used to bring down the frequency to the desired level Three counters inside 8253/4. Each works independently & is programmed separately to divide the input frequency by a number from 1 to 65536.
There are 4 port address needed for a single 8253/4, given by A0, A1, and CS

CS A1 A0 0 0 0 0 0 1 0 1 0 0 1 1

Select Counter 0 Counter 1 Counter 2 Control Reg.

70

71

8253 / 8254 Timer

Each of the three counter has 3 pins associated CLK: input clock frequency A square wave of 33% duty cycle 8253: 0 ~ 2 MHz, 8254: 0 ~ 8/10 MHz

OUT: can be square wave, or one shot GATE: Enable (high) or disable (low) the counter Data Pins: (D0 ~ D7) Allow the CPU to access various registers inside the 8253/54 for both read and write operations. RD and WR are connected to IOR and IOW of control bus.
72

Programming 8253 / 8254 Timer

Each of the three counters must be programmed separately Control byte must be first written into the control register.
The 8253/4 must be initialized before use

The programmer can not only write the value of the divisor into the 8253/4, but read the content of the counter at any given time as well All counters are down counters.`

73

Control Word for 8253/4 Timer Initialization

74

8253 / 8254 Timer

To program a given counter to divide the CLK input frequency, one must send the divisor to that specific counters register. Although all three counters share the same control register, the divisor registers are separate for each counter Example: given the port addresses for 8253/54: Counter 0: 94H Counter 2: 96H Counter 1: 95H Control Reg: 97H

75

8253 / 8254 Timer

Task1:
Program counter-0 for binary counter for mode-3 to divide

CLK0 by number 4282 (BCD)

MOV AL, 37H OUT 97H, AL MOV AX, 4282H OUT 94H, AL MOV AL, AH OUT 94H, AL => OUT0 = CLK0 / 4282

;(BCD needs H) ;(Low Byte) ;(High Byte)

76

Shape of the 8253/4 Output

Given CLK = 1.193 MHz, the clock period of input frequency is 838ns If the number N loaded into the counter is even, both high and low pulse are the same length, which is N/2 * 838ns If the number N loaded into the counter is odd, the high pulse is (N+1)/2 * 838ns and the low pulse is (N1)/2 * 838ns If N is odd, the high portion of the output square wave is slightly wider than the low portion

77

8253/54 Operation Modes

Mode 0: Interrupt on terminal count
The output is initially low, and remain low for the duration of the count if GATE=1. When the terminal count is reached, the output will go high and remain high until a new control word or new count number is loaded Width of low pulse = N * T, where T is clock period

Example:

GATE=1 and CLK = 1 MHz Clock count N = 1000

78

Mode 0 Timing Diagram

If GATE becomes low at the middle of the count, the count will stop and the output will be low. The count resumes when the GATE becomes high again This in effect adds to the total time the output is low. 79

8253/54 Operation Modes

Mode 1: HW triggered / programmable one shot
The triggering must be done through the GATE input by sending a 0to-1 pulse to it. Steps: 1) Load the count register 2) A 0-to-1 pulse must be sent to the GATE input to trigger the count
In Mode 1, after sending the 0to-1 pulse to GATE, OUT becomes low and stays low for a duration of N*T, then becomes high and stays high until the GATE is triggered again If during the activation, a retriggered happened, then restart the down counting

80

8253/54 Operation Modes

Mode 2: Rate Generator (Divide-by-N counter)
In Mode2, if GATE=1, OUT will be high for N*T, goes low only for one clock pulse, then counter is reloaded automatically, and the process continues indefinitely. Whole period: (N+1) * T

Gate Disable: 1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ). 2) If Gate goes low during an low output pulse, output is set immediately high . A trigger reloads the count and the normal sequence is repeated.
81

8253/54 Operation Modes

Mode 3: Square wave rate generator
Most commonly used
Decrement by 2
odd Even

odd

Decrement by 1, then by 2

Decrement by 3, then by 2
82

8253/54 Operation Modes

Mode 4: Software triggered strobe
Similar to Mode2, except that the counter is not reloaded automatically

In Mode4, if GATE=1, the output will go high when loading the count, it will stay high
for duration N*T. After the count reaches zero, it becomes low for one clock pulse, then goes high again and stays high until a new command word or new count is loaded

To repeat the strobe, the count must be reloaded

83

8253/54 Operation Modes

Mode 5: Hardware triggered strobe
Similar to Mode4, except that the triggering must be done with the GATE input The count starts only when a 0-to-1 pulse is sent to the GATE input If GATE retriggered during the counting, it will restart the down counting

84

8253 / 8254 Timer

85

8253 / 8254 Timer

86

8253 / 8254 Timer

87

8253 / 8254 Timer

88

8253 / 8254 Timer

89

8253 / 8254 Timer

90

8253 / 8254 Timer

91

8253 / 8254 Timer

92

8253 / 8254 Timer

93

Initialization Example
Write a program to initialize counter 2 in mode 0 with a count of C030H. Assume address for control register = 0BH, counter 0 = 08H, counter 1 = 09H and counter 2 = 0AH. Soln:
Control word:
D7 SC1 1 D6 SC2 0 D5 RW1 1 D4 RW0 1 D3 M2 0 D2 M1 0 D1 M0 0 D0 BCD 0

=B0H

Source Program:
MOV AL, B0H OUT 0BH, AL MOV AL, 30H OUT 0AH, AL MOV AL, C0H OUT 0AH, AL ; loads control word to control register ; loads lower byte of the count ; loads higher byte of the count

94

16550 - Universal Asynchronous Receiver Transmitter (UART)

95

The 16550 UART

Universal Asynchronous Receiver Transmitter
Baud rates up to 1.5 M bauds (signal elements/s)

= Data rate (bps) for binary data Compatible with Intel and other Processors Includes: - A programmable baud rate generator - 16-byte FIFO buffers at input and output to help processor deal with data bursts

96

Asynchronous Serial Data Communication

Data sent asynchronously using the format illustrated below We often use one start bit and one stop bit to frame the

data, which is usually 8-data bits with or without parity

Usually a byte of data

97

The 16550 UART: Functional Description

Totally independent Transmitter (TX) and Receiver (RX) Sections This allows communication in the following modes: - Simplex: Only TX or RX is used (one direction all the time) - Half Duplex: TX then RX (two directions at different times) - Full Duplex: TX and RX simultaneously (two directions at the same time) Can control a modem using six signals, e.g. #DSR (Data Set Ready) input, #DTR (Data Terminal Ready) output. Here the UART is the data terminal and modem is the dataset.

40 pin DIP

98

The 16550 UART: Typical Configuration

Serial to Parallel Or Parallel to Serial Converters

mP

Control
16-byte FIFO Input Buffer PS

SIN

Receiver

UART
16-byte FIFO Output Buffer PS

SOUT Data
DMA Data Transfers: Memory UART Directly Without going through the mP

Transmitter

Serial Comm. Link

Memory

99

The 16550 UART: Pin Assignments

3 I/O Address bits from Processor (Table 11-5) Chip Select Inputs (Multiple I/Ps) Master Reset (tie to mP Reset I/P) Read & Write Control inputs from mP (with complements for versatility
Address Strobe (not needed with Intels)

Data bus to Processor

40 pin DIP

Serial data INput from RX

Serial data OUTput to TX Baud rate Clock output Receiver Clock input

Crystal or External Clock Input TX ready for data. Put data into UART by DMA Interrupt Processor RX ready with data. Take data from UART by DMA

Modem Interface: Inputs & Outputs

User defined outputs

100

UARTs in the PC
Used to control the COM ports of the PC - UART at I/O address 3F8-3FF: COM Port 0 - UART at I/O address 2F8-2FF: COM Port 2

101

Programming the UART

Two Stages:

a. Initialization Dialog: (Setup) - Follows RESET - Has two steps: 1. Program the line control register (Set asynchronous transmission parameters: # of stop, data, and parity bits, etc.) 2. Program the baud rate generator for the required baud rate
b. Operation Dialog: (Actual Communication)
102

The 8 I/O Byte Locations on the UART

A2 A1 A0 Function

0
0 0 0 1 1

0
0 1 1 0 0

0
1 0 1 0 1

Receiver buffer (read data from RX) and transmitter holding (write data to TX). Also write LS byte of baud rate divisor
Interrupt enable. Also write MS byte of baud rate divisor Interrupt identification (read) and FIFO control Register (write) - Used for operation dialog programming Line control Register (Write into the line control register to program asynchronous communication at initialization) Modem control Line status LSTAT (Read the line status register to see if TX or RX are ready and to check for errors )

1
1

1
1

0
1

Modem status
Scratch
103

1. Programming the Line Control Register a. Initialization I/O Address: A2 A1 A0 = 011

Dialog Programming

DL bit must be set before you can load the divisor for the baud generator

Parity Control See next slide

Data Length = 5 bits Data Length > 5 bits

See Table on next slide

A break is a minimum of 2 frames of 0s

104 To allow programming The baud rate generator

The 3 Parity Control Bits in the Line Control Register

ST 0 0 0 0 1 1 1 1 P 0 0 1 1 0 0 1 1 PE 0 1 0 1 0 1 0 1 Function No parity Odd parity No parity Even parity Undefined Send/receive 1 (send 1 in place of the parity bit) Undefined Send/receive 0 (send 0 in place of the parity bit)
105

2. Programming the Baud rate Generator

Baud rate is programmed by loading a 16-bit divisor for the crystal oscillator (or external input) frequency into the I/O port addresses: {A2 A1 A0} = 000: LS Byte of divisor {A2 A1 A0} = 001: MS Byte of divisor Divisor value is determined by the Oscillator frequency and the baud rate required: Divisor = Oscillator frequency / (16 * Baud rate) Table shows divisor values required for various baud rates for osc frequency = 18.432 MHz
Baud Rate 110 Divisor Value 10,473

300
1200 2400 4800 9600 19,200 38,400 57,600 115,200

3840
920 480 240 120 60 30 20 10

106

(Active Low)

107

;Initialization dialog for Figure 11-45 ;Baud rate 9600, 7 bit data, odd parity, 1 stop bit LINE EQU 0F3H ; A2 A1 A0 = 011 for the Line Control Register LSB EQU 0F0H ; A2 A1 A0 = 000 for LSB of divisor MSB EQU 0F1H ; A2 A1 A0 = 001 for MSB of divisor FIFO EQU 0F2H ; A2 A1 A0 = 010 for the FIFO Control Register INIT PROC NEAR MOV AL,10001010B OUT LINE,AL ; Enable Baud rate programming See slide 108

; program Baud 9600 ; Divisor = 120d (see Table on slide 110) MOV AL,120 OUT LSB,AL MOV AL,0 OUT MSB,AL MOV AL,00001010B Must write this OUT LINE,AL
into FIFO Register to enable communication and operation dialog programming

; LSB of divisor

; MS Byte of divisor
;program 7 bit data, odd ;parity, 1 stop bit ;(& disable baud rate programming?) ;enable transmitter and receiver ;by writing into the FIFO control Reg.
108

MOV AL,00000111B OUT FIFO,AL RET

INIT

ENDP

16550 FIFO Control Register (Write)

I/O Address: A2 A1 A0 = 010

Required to enable actual communication (Operation Dialog)

109

b. Operation Dialog Programming

16550 Line Status Register (LSTAT)

I/O Address: A2 A1 A0 = 101
Before reading data from receiver, ensure RX has data [DR (bit 1) = 1]

Error status bits Any being 1 indicates An error

Before writing data for transmission, Ensure TX is ready to take it [TH (bit 5) = 1]

110

111

D/A and A/D Converters

Interfacing with 8086

112

Digital to Analog (D/A) Converters

D/A converter converts the binary word into corresponding Voltage or Current.

The DAC is used in applications

Digitally controlled gains, Motor speed controls,

Programmable gain amplifiers.

Compact Disc Audio & Video Players.

113

Op-Amp D/A Converter (DAC)

This DAC is based on summing point Op-amp. The output analog voltage generated is proportional to the binary value of the input digital voltage. The Binary weighted Resistors Produce Binary currents which are summed by the Op-amp to produce a proportional output voltage.

4-bit 114 DAC

MC1408 : 8-bit D/A converter

The MC1408-8 is an 8-bit monolithic digital-to-analog converter which provides
High-speed performance Low cost. Resolution: 1 part in 256.

The output current is a linear product of an 8-bit digital

word and an analog reference voltage.

115

MC1408 Block diagram

116

MC1408 Description

The MC1408-8 consists: 8 high-speed current switches:

The switches are non-inverting in operation. A high state on the input turns on the specified output current component.

R-2R ladder:
The R-2R ladder divides the reference amplifier current into binaryrelated components, These are fed to the remainder current which is equal to the least significant bit. The maximum output current is 255/256 of the reference amplifier current.
117

MC1408 Description
Reference current amplifier:
The reference voltage source supplies the full reference current through R14 resistor for Reference current amplifier

Typical Performance Characteristics:

118

Instruction Timing and Delay Loops

The rate at which an instruction is determined by the Processor Clock.

For 8086, the Clock frequency is 5 MHz and the Clock cycle takes 0.2us.
Each Instruction takes some time for Execution.

Examples:
MOV AX,BX takes two clock cycles (0.4us). DAA takes four clock cycles (0.8us).

119

Calculation of Delay Loop

When a delay need to be inserted in a program,
Initialize CX register according to delay time. LOOP instruction be used to produce the Delay. NOP can be used in between the Loop.

Calculation:
Calculate the clock cycles for each instruction inside and outside the loop.

Find the no. of clock cycles according to delay time and processor clock.
Equate these two values to obtain the CX initialize value.

120

A/D Converter
A/D Converter produces digital word which represents the magnitude of analog voltage or current. Specifications: Resolution Accuracy: The difference between a measurement reading and the true value of that measurement Linearity Conversion Time :
The Conversion Time of A/D Converter is more than D/A converter.

121

Parallel Comparator A/D Converter

122

Parallel Comparator A/D Converter

It is a N-bit Flash ADC using Parallel Comparators. The Voltage divider sets the reference voltages on the inverting inputs of the comparator. If the Vin applied to non-inverting terminal is more than the Vref at the inverting terminal, then Vout is High and Vice-versa. The Comparator output is given Encoder to produce actual digital word. Advantage:
Less Conversion time : Propagation delay of Comparators.

Disadvantage:
Low Resolution : No. of Comparators (2n-1) required are more.

123

Dual Slope A/D Converter

124

Dual Slope A/D Converter

When Control switch is towards the input positive Voltage,
The capacitor charges linearly with rate of Vin/RC for fixed time Produces a negative, variable-slope ramp. Comparator Output is High. And gate enables 1 MHz clock into counter chain with fixed counts.

After fixed time, the Control switch is towards the negative reference Voltage.
Resets the counter values to zero. The capacitor then discharges linearly with rate of Vref/RC for variable time Produces a positive, fixed-slope ramp.

125

Dual Slope A/D Converter

When Output voltage crosses 0v, Comparator Output is Low. And gate disables 1 MHz clock into counter chain. Then the counter runs, yielding a count proportional to the input voltage.

This method is commonly used with voltmeters and other test equipment. Advantages:
Higher resolution Higher accuracy Lower cost Good noise immunity Slow Conversion Time

Disadvantages:

126

Successive Approximation ADC

127

Successive Approximation ADC

This ADC is the most commonly used in many applications. Successive Approximation ADC Components:
D/A converter Comparator Success-approximation register.

Conversion Process:
The bits of the D/A converter are enabled one at a time, starting with the MSB. As each bit is enabled, the comparator produces an output. It indicates whether the analog input voltage is greater or less than the output of the D/A converter.

128

Successive Approximation ADC

If the D/A output is greater than the analog input, the comparator output is LOW and the bit is set LOW.

If the D/A output is less than the analog input, the comparator output is HIGH and the bit is set HIGH.
This process is repeated for each bit.

Properties
Reliable Capable of high speed

Conversion time is clock rate times number of bits.

129

Generic 4-bit Successive- Approximation ADC

130

Summary of Convert Types

131

Interfacing different A/D Converters

Parallel Comparator A/D Converter:
The A/D conversion is much faster than a processor could read them. So, DMA (Direct Memory Access) is used to store directly the output

into memory irrespective of the processor.

Dual Slope A/D Converter:

Processor reads the digital output by polling method. It polls the bit corresponding to strobe line.

When it is high, processor puts the data into memory.

This polling process is repeated until all the data is transferred.

132

Interfacing different A/D Converters

Successive Approximation ADC:
Before the A/D conversion starts
The Microprocessor sends SOC (Start of Conversion) signal to ADC.

After the conversion is over,

The ADC sends EOC (End of Conversion) signal The result is ready at the output buffer of the ADC.

Conversion Delay of the ADC.

The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal

These tasks are carried out by the Microprocessor using 8255 I/O ports.

133

A/D Converter - ADC 0808

ADC 0808 is a 8-bit CMOS, Successive Approximation A/D Converter. The conversion delay is 100s at a clock frequency of 640 KHz.

It has a 3:8 analog multiplexer

At a time, eight different analog conversions by using 3 address lines. The microprocessor may drive these lines using output port lines in case of multichannel applications.

It is a Uni-polar analog to digital converter

they are able to convert only positive analog input voltage to their digital equivalent.

134

ADC 0808 Block Diagram

135

Interfacing ADC 0808 with 8086

136