DSP FUNDAMENTALS

Analog v/s Discrete-time v/s Digital

System
A physical device performs an operation on the signal. Any process that exhibits cause and effect relation can be called a system. A system will have an input signal and output signal. The output signal will be a processed version of the input signal.

System

Analog to digital conversion

A digital signal can be obtained from the analog signal by using an analog to digital converter.

Sample
Continuous time continuous amplitude input signal

Quantize
discrete time discrete amplitude signal

Encode
Digital output signal

Discrete time continuous amplitude signal

Signal Processing
The operation performed by the system on the signal is called signal processing. For e.g.: when we pass the signal through filter we can say that the signal is processed.

Signal Processing algorithms

Convolution (mixing of signals) Correlation (comparison of signals) Transformation of signals (e.g. time to frequency domain) Filtering of signals

CONVOLUTION
Convolution is a mathematical way of combining two signals to form of a third signal.

n)

y(n)
Linear system h(n)

CORRELATION
Correlation gives a measure of similarity between two data sequences. In this process, two signal sequences are compared and the degree to which the two signals are similar is computed.

At present, everything is becoming digital these days, DSP Filters, DSP Modems, DSP based Motor Controllers, DSP based UPS, DSP based transceivers and more. Digital representation of signals over their analog counterparts have many advantages.

* * * * * *

Fewer Components Stable, deterministic performance Wide range of applications No filter adjustments Filter with much closer tolerances Adaptive filters easily implemented

Introduction about DSP Processor

Digital signal processers are microprocessors specially

designed for efficient implementation of digital signal processing system.

The DSP gained popularity in 1960s.
The pioneers in developing digital signal processor are Texas

Instruments & Analog devices of USA.

Texas Instruments has released TMS 320 series of digital

signal processors.

Conti
The TMS320 family of processors include four basic type

of processors 1.16 bit fixed point processor 2.32bit floating point processors 3.VLIW Architecture processors 4.Multiprocessors DSPs

Fixed point processor & Floating point processor

Fixed point processors are low power and low cost

devices and they can operate at high speed due to simple architecture.
The floating point processors are large dynamic range,

wider instruction word size and support more addressing modes

VLIW Architecture Processor & Multiprocessor Architecture Processor

VLIW processor employ instruction level parallelism

in which many instructions are issued at the same time and are executed in parallel by multiple execution unit. Multi-processor provide parallel processing capability by integrating multiple DSPs on a single piece of silicon. These two processor supports both fixed point and floating point computation.

Inside a DSP?

Computer Engine

Input / Output Serial ports Timers Host ports I/O External ports connects Link ports
to outside world

Program Memory

Data Memory

INSIDE A DSP ENGINE?

Architecture of the Digital Signal Processor

DSP LEADING MANUFACTURERS

TEXAS INSTRUMENTS (TI) ANALOG DEVICES (ADSP) MOTOROLA

TMS320CXXXX DSP Family

First Generation (1982)

In 1982 TI introduces its

first programmable DSP 16-bit fixed-point Harvard architecture Accumulator Specialized instruction set Operating at 5 MIPS EXAMPLE : TMS320C10

5MIPS
28

Second Generation (1987)

24-bit data, instructions

1988 First Floating Point

DSP (C3X) 3 memory spaces (X, Y, P) Modulo addressing EXAMPLE : TI- TMS320C3x MOTOROLA DSP5600 ADSP 2100, AT & T DSP16A, TMS320C50
20MIPS
29

Third Generation (1995)

Enhanced conventional DSP architectures

3.0 or 3.3 volts

More on-chip memory
160MIPS

Application-specific function units in data path or

as co-processors More sophisticated debugging and application development tools

EXAMPLE : MOTOROLA DSP56301, TI TMS320C5416

30

Fourth Generation (1998)

32 Bit floating point.

Designed for REAL TIME PROCESSING easily.

Operating Core Voltage : 1.8V

DSC (TMS320F2812) for Motor Control Applications VLIW-like architectures, achieve top performance via high parallelism and increased clock speeds EXAMPLE : TI TMS320C6713, ADSP BLACKFIN

600MIPS
31

DSP TEXAS INSTRUMENTS FAMILY

TMS320C6000 C62X,C64X,C67X DSPs TMS320C2000 C24X,C28X DSPs
Control Optimized

TMS320C5000 C54X,C55X DSPs

Power Efficient
OMAP C55X+ARM

High Performance

www.ti.com

TMS320F240 16 Bit Fixed point 20 MIPS 544 x 16 Bit RAM 3 GP Timers

TMS320F2407A 16 Bit Fixed point 40 MIPS 2.5k x 16 Bit RAM 4 GP Timers

TMS320F2812 32 Bit Fixed point 150 MIPS 18k x 16 Bit RAM 7 GP Timers

SPI & SCI Serial ports

12 PWM Channels 16 Channel ADC @ 6 microsec conversion time

SPI, SCI & CAN Serial ports

16 PWM Channels 16 Channel ADC @ 0.5 micro sec conversion time

SPI, SCI & CAN Serial ports

16 PWM Channels 16 Channel ADC @ 200 ns conversion time

TMS320F2812
32 Bit Fixed point 150 MIPS 18k x 16 Bit RAM

TMS320C6713 + FPGA
32 Bit Floating point 1300 MFLOPS 4MB RAM
FPGA Based (User Programmable)
FPGA Based (User Programmable)

7 GP Timers
SPI, CAN Serial ports 16 PWM Channels

More than 16 PWM Channels

FPGA Based (User Programmable)

16 Channel ADC @ 12.5 MSPS 16 Channel ADC @ 320 MSPS

2 Simultaneous sampling
Fixed Hardware User cannot change the hardware configurations

8 Simultaneous sampling
Flexible Hardware User can change & configure any new hardware through software programming like 16/32 bit timer

Architectural Features of DSPs

Data path configured for DSP Fixed-point and floating point arithmetic

MAC- Multiply-accumulate
Multiple memory banks and buses Harvard Architecture Multiple data memories and busses Specialized addressing modes Bit-reversed addressing, Circular buffers

Specialized instruction set and execution control

Support for fast MAC Fast Interrupt Handling Specialized peripherals for DSP

TMS320C55xxA DSP Block Diagram

CHARACTERISTICS OF TMS320C50
Very flexible instruction set. Inherent operational flexibility. High speed performance. Innovative, parallel architecture design. Cost - effectiveness.

TMS320C50 KEY FEATURES

Operating at 3.3v . Speed 50 MIPS. Source code compatibility with C1X, C2X, C2XX More on chip peripherals Good CPU. Specialized instruction set .

ON CHIP PERIPHERALS
Clock generator
Hardware timer Software programmable wait-state generators Parallel I/O ports Host port interface

Serial port
Buffered serial port TDM serial port.

REGISTERS
AR

CIRCULAR BUFFER REGISTER (SR1,CBER1,CBSR2,CBER2,CBCR )

HPI REGISTER ( HPIC , HPIA )

INTRUCTION REGISTER ( IREG )

PRODUCT REGISTER ( PREG )

TEMPORARY REGISTER ( TREG0, TREG1, TREG2 )

OMAP PROCESSOR

C6000

TMS320C6000 DSP Platform

This has got 3 series of DSP Processor family.

TMS320C62XX TMS320C67XX

32 Bit Fixed Point DSP

TMS320C64XX

32 Bit Fixed Point DSP

32 Bit Floating Point DSP

TMS320C6000 PLATFORM ROADMAP

'C6000 System Block Diagram

External Memory P E R I P H E R A L S
Internal Memory

Internal Buses

CPU

Regs (A0-A15)

Regs (B0-B15)

.D1 .D2
.M1 .M2 .L1 .L2

.S1 .S2

CPU Contains,
Program fetch unit. Instruction dispatch unit. Instruction decode unit. Two data paths, each with four functional units. 32 32 bit register. Control register. Control logic Program fetch , instruction dispatch (C64X only)and instruction decode units can deliver up to eight 32 bit instructions to the functional units for every cpu clock cycle. Processing of instruction occur in each of the two data path A and B. Each path contain four functional unit (.L , .S, .M and .D) It has 16 32 bit general purpose register for C6713. A control register file provides the means to configure & control various processor operation.

TMS320C6711 / C6712 / C6713 DSP Block Diagram

67xx

Highest-Performance Floating-Point Digital Signal Processor

TMS320C6713
* Eight 32-Bit Instructions/Cycle

* 32/64-Bit Data Word

* 225-MHz Clock Rates

* 4.4-, 6.7-ns Instruction Cycle Time

* 1800 MIPS/1350 MFLOPS * Rich Peripheral Set, Optimized for Audio * Highly Optimized C/C++ Compiler

TMS320C6713

C6000 Internal Buses

Program Addr
Internal Memory

Program Data
Data Addr - T1 Data Data - T1

PC A
regs

External Memory

Data Addr - T2 Data Data - T2

B
regs

DMA Addr - Read

DMA Data - Read
Peripherals

DMA Addr - Write

DMA Data - Write

DMA

GENERAL PURPOSE REGISTER

Two general purpose register file (A and B) in C6713 data path.

Each of these file contain 16-32 bit register files : A0 A15 for file A B0 B15 for file B
General purpose register can be used for data,data address pointer, or condition register. Supports data ranging in size from packed 16 bit data through 40 bit fixed point and 64 bit floating point data. Values larger than 32 bits, such as 40 bit long and 64 bit float quantities are stored in register pair. In these 32 LSBs of data are placed in an even-numbered register and the remaining 8 or 32 MSBs in next upper register (which always an odd numbered register)

TIMER
The C6000 devices have 32-bit general-purpose timers that are used to perform these functions: Time events Count events Generate pulses Interrupt the CPU Send synchronization events to the DMA/EDMA controller.

GPIO
The GPIO peripheral provides a dedicated set of general-purpose input/ output signals to the C6000 device.

Transitions on these signals can be used to generate interrupts to the CPU and synchronization events to the EDMA.

Interrupt Selector
The C6000 peripheral set produces interrupt sources.

The interrupt selector allows the user to choose which interrupts their system needs.
The interrupt selector also allows you to change the polarity of external interrupt inputs.

Power-down
The power-down logic allows reduced clocking to reduce power consumption. Most of the operating power of CMOS logic dissipates during circuit switching from one logic state to another. By preventing some or all of the chips logic from switching, you can realize significant power savings without losing any data or operational context.

HOST PORT INTERFACE

The HPI is a parallel port through which a host processor can directly access the CPUs memory space.

The host device has ease of access because it is the master of the interface.
The host and the CPU can exchange information via internal or external memory. In addition, the host has direct access to memory-mapped peripherals.

EXPANSION BUS
The expansion bus is a replacement for the HPI, as well as an expansion of the EMIF. The expansion provides two distinct areas of functionality (host port and I/O port) which can co-exist in a system. It can operate in either Asynchronous slave mode (similar to HPI). Synchronous master/slave mode. It allows the device to interface to a variety of host bus protocols.

McBSP
The multichannel buffered serial port (McBSP) is based on the standard serial port interface found on the TMS320C2000 and C5000 platform devices. In addition, the port can buffer serial samples in memory automatically with the aid of the DMA/EDMA controller. It also has multichannel capability . it provides these capabilities: Full-duplex communication Double-buffered data registers that allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to industry-standard codecs, analog interface chips (AICs), & other serially connected analog-to-digital (A/D) ,digital-toanalog (D/A) devices.

Boot Configuration
The TMS320C6000 devices provide a variety of boot configurations. That determine what actions the DSP performs after device reset to prepare for initialization. It include loading in code from an external ROM space on the EMIF and loading code through the HPI/expansion bus from an external host.

PCI
The PCI module supports connection of the C6000 device to a PCI host via the integrated PCI master/slave bus interface.

C67xx Memory
0000_0000

4K Program Cache
0180_0000

64KB Internal

64K
CPU

On-chip Peripherals

Prog / Data (Level 2) 8000_0000

0 1 2 3

128MB External 128MB External 128MB External 128MB External

4K Data Cache

9000_0000
A000_0000 B000_0000 FFFF_FFFF

MEMORY
On chip (internal ) memory is organized in separate program and data space.(Harvard architecture Off chip (external ) memory is used, these space are unified on most device to a single memory space via External Memory Inter-Face (EMIF). C6713 have : Two 32-bit internal port to access internal data memory. one 32-bit internal port to access internal program memory. EMIF: The EMIF supports a glue less interface to several external devices, including the following: Synchronous burst SRAM (SBSRAM) Synchronous DRAM (SDRAM) Asynchronous devices, including SRAM, ROM, and FIFOs An external shared-memory device.

PROGRAM MEMORY
The program memory controller performs the following tasks:
Performs CPU and DMA requests to internal program memory and the necessary arbitration. Performs CPU requests to external memory through the external memory interface (EMIF). Manages the internal program memory when it is configured as cache.

DATA MEMORY
Data memory is accessed through the data memory controller, which controls the following functions: CPU and DMA controller accesses to the internal data memory, and performs the necessary arbitration. CPU data access to the EMIF. CPU access to on-chip peripherals. The internal data memory is divided into 16 bit wide banks. Arbitration between the CPU and DMA controller independently for each bank. It allowing both sides of the CPU and DMA to access different memory location simultaneously without contention. A 256-bit-wide path is provided from to the CPU to allow a continuous stream of eight 32-bit instruction for maximum performance

DMA Controller.,
The DMA controller transfers data between address ranges in the memory map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel. The data memory controller services all CPU and DMA controller data requests to internal data memory.

EDMA Controller: The EDMA controller performs the same functions as the DMA controller. The EDMA has 16 (C621x/C671x) or 64 (C64x) programmable channels, as well as a RAM space to hold multiple configurations for future transfers.

'C6000 Peripherals
XB, PCI, Host Port GPIO Internal Memory

External Memory

EMIF McBSPs Utopia DMA, EDMA (Boot) Timers VCP TCP PLL

Internal Buses

CPU

Register Set A

Register Set B

.D1 .D2
.M1 .M2 .L1 .L2

.S1 .S2

Peripheral Signals

FEATURES OF TMS320C6713
It can handle 1800 MIPS. Highly optimized C/C++ compiler. Two 32-bit general-purpose timers. Eight 32-bit instruction/cycle 32/64 bit data word. Execute up to eight instruction per cycle for up to ten times the performance for other DSPs (VLIW). 8/16/32- bit data support, providing efficient memory support for a variety of applications. 40-bit arithmetic options, which add extra precision for vocoders and other computationally intensive application Etc..,

Development Tools
CODE COMPOSER STUDIO

It includes

Assembler Linker Simulator C/C++ compiler Debugger

TI APPLICATIONS GUIDELINE
C2000 C5000 C6000 OMAP

Audio
Biometrics

Digital Control Telecom

Video & Imaging

Blackfin Processor
High Performance for Networking and Digital Imaging

Blackfin Processors employ a

dual-MAC DSP core

It includes efficient RISC MCU

system control functionality

This core, developed jointly

between Analog Devices and Intel Corporation

Embedded features to support

efficient use of a Real-Time Operating System (RTOS)

ADSP-21xx and Mixed Signal DSPs

Code compatible DSP excellence Fixed point 16-bit DSPs. The family offers a

wide range of speed and performance options. ADSP-21xx DSPs are ideal for
Telephony Data acquisition Industrial automation Motor control Optical networking control Portable instrumentation

Audio solutions Biometrics system solutions Telecom system solutions Wireless terminal Applications Video and imaging system solutions Network control Applications Digital control solutions

DSP BASED DIGITAL CONTROL SOLUTIONS

Compressors Industrial automation (UPS) systems Automotive braking Power supplies Electric metering

Electronic cooling systems

Consumer goods Printers and copiers Hand-held power tools

Automotive steering
Modern Motor control drives

DSP in Motor Control Applications

DSPs to improve the control efficiency of electric

motors. The introduction of brush less dc motors has however increased the level of complexity in controlling these applications. DSPs implement sensor less control, which calculates velocity and position in real time from known current and voltage values, and field-oriented control, which converts all variables to a coordinate system relative to the magnetic field of the rotor. DSPs gave low power,high speed & reduce the complexity of circuit design DSP can easily implement digital PWM techniques like space vector modulation

DSP WITH FPGA BASED POWER ELECTRONICS CONTROL SOLUTIONS

The TMS320C6713 highest performance DSP with a XILINX VIRTEX FPGA based PWM generation & XILINX SPARTAN 3 FPGA based high speed ADC capture provides modern control solutions for power electronics applications
High performance 32 bit floating point DSP High speed memory

USB & other serial embedded interfaces

Virtex FPGA for PWM generation SPARTAN 3 FPGA interface for 16 channel ADC capture with 320 million samples per second

Isolated Analog & Digital interface

TMS320C6713 DSP WITH XILINX VIRTEX FPGA BASED SYSTEM FOR MODERN DRIVES
TMS 320C6713
(1300 MFLOPS) USB

PC

SPARTAN FPGA

SPARTAN FPGA

Virtex FPGA

40 MHZ ADC

40 MHZ ADC

40 MHZ ADC

40 MHZ ADC

PWM Outputs

16 Channel ADC

THANK YOU ALL