Advanced Embedded Memory Testing and Analysis Using Built In Self Test

Presented by B.S.N Kishore 11741D5705 M.tech(VLSI Systems Design) Intell Engineering College,Anantapuram Under the guidance of Smt.M.Mahitha M.tech Assistant Professor Department of ECE

AIM
To detect for faults in embedded read only memories.

INTRODUCTION
Different types of faults occur like stuck at faults,

transition faults ,bridging faults etc.

It is imperative to deploy effective means of testing

and diagnosing non volatile memory failures.

Limitations of Existing System

The earlier method made use of algorithms based

diagnosing like March a and march b .

Hardware area and hardware cost is increased. Speed of is also less.

BUILT IN SELF TEST(BIST)

BIST(cont.)
BIST is a design for testability technique in which

testing is accomplished through built in hardware features.

Output response analyzer indicates that the expected

response of the CUT is to be compared with the reference response i.e. the golden response.

PROJECT IMPLEMENTATION

The different modules that are implemented are: Bist Controller ROM Array Row Selector Column Selector Combined Row and Column Selector Signature Register

BASIC TEST ARCHITECTURE

BIST CONTROLLER
BIST controller has a control on both test pattern

generator and output response analyzer

BIST controller consists of the reference response

where it sends to the signature register.

It generates row and column addresses that is sent to

the decoder.

DETERMINISTIC PARTITIONING
The deterministic partitioning helps rows and

columns decomposed into 2 partitions of same size where n = 0.5 log v

Different groups of partitions are formed thus, such

that the numbers are repeated in other partitions.

ROW SELECTIONS

ROW SELECTIONS(CONT.)
The row selector comprises of the upcounters for

partitions,groups,the LFSR and the offset counter. The circuit implements the following formula
r =Sk+(p(gk)),k=0,1,...,P1.

For 16 rows forming 4 partitions( n =2) ,and with group 3 and partition 2,data is compacted from rows 2,5,11,12

ROW SELECTIONS (CONT.)

COLUMN SELECTIONS

PHASE SHIFTERS FOR COLUMN PARTITIONING

COLUMN SELECTIONS(CONT.)
There is a need for two 1 out 4 column decoders and

one phase shifter connected to the decoder selecting bits.

The addresses that are observed by the column

decoder 0 result in selection of columns 0,5.

The addresses that are received by column decoder 1

result in selection of column 14 and 11.

COLUMN SELECTIONS(CONT.)

COMBINED ROW AND COLUMN SELECTIONS

COMBINED ROW AND COLUMN SELECTION(CONT.)

The Combined row and column selection helps to find

the cells where rows and columns intersect.

They help to find single cell failures through

employing signature register injector network.

SIGNATURE REGISTER

SIGNATURE REGISTER(CONT.)
Signature register is used to collect the test responses

arriving from selected memory cells It compares the responses with that of golden response and failing rows and/or columns are detected The register can be reset at the beginning of every run over address space and the content of the register is downloaded once per run .

SIGNATURE REGISTER INJECTOR NETWORK

a)single stuck at column and single stuck at row failure b)Error free response c)Erroneous response.

Row Selector simulation result

Column Selector simulation result

Combined row and column selector result

CONCLUSIONS
The presented approach allows uninterrupted

collection and processing of test responses at system speed.

The new combined selection logic allows to collect test

results in parallel leading to shorter test time without compromising quality of diagnosis and it clearly conforms high accuracy of diagnosis .

FUTURE SCOPE
This method can be developed further to achieve

testing of more bits at once so that productivity increases further.

The diagnositc data that needs to be scanned out

during ROM test may be decresed further.

REFERENCES
Digital Systems Testing and Testability,Abramovici,Friedman,Jaico Press. D. Appello, V. Tancorre, P. Bernardi, M. Grosso, M. Rebaudengo, and M. Sonza Reorda, Embedded memory diagnosis: An industrial workflow, inProc. ITC,2006 J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, Enabling embedded memory diagnosis via test response compression, inProc. High performance memory testing:Design principles, fault modelling and self test R.D Adams http://nptel.iitm.ac.in http://www.edaboard.com/search.php?searchid=2570410

THANK YOU!