COE 381 MICROPROCESSORS

UNIT 2 MEMORIES

Chapter Objectives
Stored Program Concept Addressing

Address Decoding Using Memory Chips

Commodity Memories
Timing

Chapter Objectives
Reality of Memory Decoding Filling the Memory Map

Memory Map Details

Endianness

Separate I/O Address Space Memory Hierarchy

Chapter Objectives
Caches
Read Only Memory (ROM) Punch Cards Harvard Architecture Current Memory Technology ROM / PROM

Chapter Objectives
More Electrostatic Memories
More Magnetic Memories Full Address Decoding

Magnetic Memories

Optical Memories Partial Address Decoding

Chapter Objectives
Designing Address Decoders
Address Decoding with Random Logic Address Decoding with m-line-to-nline Decoders

Address Decoding with PROM

Address Decoding with FPGA, PLA and PAL

SECTION 1:

MEMORY

The Stored Program Concept

The concept of a stored program:
Instructions can be represented by numbers and stored in the same way as data.

E.g. a bit pattern 01000101 represents

the number 69 or the letter E or the an instruction for, say, multiplication

The Stored Program Concept cont

The same memory locations may be used as instructions and data (though rare)
Question: what is the difference between the von Neumann architecture and the stored program concept?

Determining Addressable Memory

A processor with 12-bit address bus
can address up to 4Kwords of memory.

e.g. ARM which produces byte addresses

has 32-bit address bus and hence capable of addressing up to 232 separate bytes.

Commodity Memories
All von Neumann computers need memory
Small memories (a few Kbytes) are often on-chip Large memories could be in one or more modules

Several types of memory exist

cost trade-offs vary according to the system requirement

Commodity Memories (2)

D-type flip-flops
Convenient for synchronous logic (e.g. FSMs) Very large area per bit

Transparent latches
Okay for logic but not as convenient
Smaller than D-types, but still large

Commodity Memories (3)

SRAM
Small area per bit

Need (shareable) interface logic Simple to use

DRAM
Very small area per bit

Need considerable interface logic Many awkward timing constraints

Memory Chips

The memory device shown is a 628512. This is a 4Mbit SRAM chip organized as 512 Kwords of 8 bits each. It therefore requires nineteen address lines and eight data lines.

Memory Chips (contd)

The following table defines the memory chips behaviour.

Points to note:
All the control signals are active low

If the chip is not selected (/CS = H), nothing happens Write enable overrides read operations The data bus is bidirectional (either read or write saves pins)

Timing Issues
When accessing a memory location: ensure that
the correct data is accessed at the correct location no other memory locations are involved

It is important that the address is stable during the write operation

else other locations may also be affected

Timing (2)

The timing diagram

Timing Issues (3)

Write strobe
a logical AND of the write enable and chip select signals both must be active for data to be written.

The timing diagram on the previous slide is only one of the possible approaches to strobing memory.

Timing (4)
Different processors (& different implementations) encode timing differently. This is okay, as long as timing is included somewhere on the datasheet.

Addressing
Some definitions: Byte now standardized as eight bits. Nibble four bits or half a byte

Word the natural size of operands, which varies from processor to processor (16 bits in MU0, 32 bits in ARM). Usually the width of the data bus.

Addressing (2)
Width the number of bits in a bus or a register Address range the number of elements which can be addressed.

Type what the data represents.

Addressing (3)
The memory only performs one operation at a time. A memory operation requires the answers to some questions:
Do what? Control (read or write) With what? Data Where? Address

Address Decoding
A memory address may not always refer to one location The ARM processor example

Address Decoding (2)

Addresses are decoded to the minimum addressable size (usually a byte)

In ARM the LSB used by the address decoder is A[2]

A[1] and A[0] act as byte selectors, which will be ignored when performing word-wide operations

Byte Access
Bus addressing is normally written in the format N[X:Y] Notice that when the processor reads word 00000000 it receives data on all its data lines (D[31:0]).

Filling the Memory Map

The ARM processor
has a 32-bit word length.

produces a 32-bit byte address. can perform read and write operations with 32-, 16- and 8-bit data.

Filling the Memory Map (2)

The normal design for the memory system would therefore be a space of 230 words of 32bits each This could be populated, using the 128K8-bit RAM chips Four RAMs (i.e. 512Kbytes)= 128KWords A total of 230/217 = 213 =8192 RAM chips required

Filling the Memory Map (3)

Memory Map Details

The memory is coarsely divided into areas with different functions Some area are left blank Some physical devices can appear at several different addresses The I/O space is unlikely to be full

Separate I/O Space

I/O access patterns different from memory accesses
I/O access being rarer

Separate address space for I/O (e.g. x86 architecture)

Cleaner address space left just for true memory I/O space referenced with different instructions (e.g. IN and OUT )
limited addressing modes and, possibly, a smaller address range

Same bus (with an added address line IO/mem)

Endianness
Endianness refers to the way sub-elements are numbered within an element
e.g. the way bytes are numbered in a word.

Two types Little endian and Big endian

By convention the bytes-in-a-word definition tends to dominate.

Little Endian Addressing

The least significant byte is at the lowest address. e.g. Storing a word (say, 12345678) at a range of locations starting from address 00001000 in a 32bit byte-addressable address space gives results:
Address 1000 contains byte 78 Address 1001 contains byte 56 Address 1002 contains byte 34 address 1003 contains byte 12

Little Endian Addressing (2)

Displayed as bytes, a memory dump would look like: 00001000 78 56 34 12 Performing a byte load at the starting address would return: 00000078

Big Endian Addressing

The most significant byte is at the lowest address.
Using the same word address (00001000) for the same word (12345678):
Address 1000 contains byte 12 Address 1001 contains byte 34 Address 1002 contains byte 56 Address 1003 contains byte 78

Big Endian Addressing (2)

Displayed as bytes, a memory dump would look like: 00001000 12 34 56 78 If a byte load was performed on the same address the result would be: 00000012

NB: Choice of endianness in a given processor is arbitrary.

Harvard Architecture
Stored program computers with separate instruction and data buses The Harvard architecture logically separates the fetching of instructions from data reads and writes Its real purpose is to increase memory bandwidth

Harvard Architecture (2)

Disadvantages:
the available memory is pre-divided into code and data areas it is hard or impossible for the code to modify itself more wiring (pins, etc.)

SECTION 2

ADDRESS DECODING STRATEGIES

Address Decoding
Although memory space is said to be flat, it does not mean the physical implementation is homogenous

Different portions of memory are used for different purposes: RAM, ROM, I/O Even if all the memory was of one type, we still have to implement it using multiple ICs

Address Decoding
This means that for a given valid address, one and only one memory-mapped component must be accessed Address decoding is the process of generating chip select (CS*) signals from the address bus for each device in the system

Arrangement of 2KB Memory Blocks

The address bus lines are split into two sections the N most significant bits are used to generate the CS* signals for the different devices the M least significant signals are passed to the devices as addresses to the different memory cells

Decoding Logic for M1 and M2

000 000 000 7FF 000 800 000 FFF 001 000

Address decoding methods

There are two types of address decoding: Full address decoding Partial address decoding

Full address decoding

All the address lines are used to specify a memory location Each physical memory location is identified by a unique address

Recall

An Example using Binary Decoder

Lets assume a very simple microprocessor with 10 address lines (1KB memory) We wish to implement all its memory space using 128x8 memory chips

We will need 8 memory chips (8x128=1024)

Solution using Decoding Table

Device Device Mem. Size (m) MEM0 128B = 27 = $80 MEM1 128B = 27 = $80 MEM2 128B = 27 = $80 MEM3 128B = 27 = $80 MEM4 128B = 27 = $80 MEM5 128B = 27 = $80 MEM6 128B = 27 = $80 MEM7 128B = 27 = $80 m-1 $7F $7F $7F $7F $7F $7F $7F $7F

Solution using Decoding Table

Device Start Address MEM0 $000 MEM1 $080 MEM2 $100 MEM3 $180 MEM4 $200 MEM5 $280 MEM6 $300 MEM7 $380 End Address $07F $0FF $17F $1FF $27F $2FF $37F $3FF

Decoding Table
Device A9 MEM0 0 MEM1 0 MEM2 0 MEM3 0 MEM4 1 MEM5 1 MEM6 1 MEM7 1 A8 0 0 1 1 0 0 1 1 A7 0 1 0 1 0 1 0 1 A6 A5 A4 A3 A2 A1 A0

Solution
We will need 3 address lines to select each one of the 8 chips Each chip will need 7 address lines to address its internal memory cells

An Example using Random Logic

Lets assume the same microprocessor with 10 address lines (1KB memory) However, this time we wish to implement only 512 bytes of memory We still must use 128-byte memory chips Physical memory must be placed on the upper half of the memory map

Solution using Decoding Table

A More Difficult Example

Device Description Device Name Amount of Memory to Address . 4KB 4KB 8KB 2 bytes 2 bytes

ROM chip RAM chip ROM chip Peripheral 1 Peripheral 2

ROM1 RAM ROM2 PERI1 PERI2

Device Memory Mapping

Device ROM1 RAM ROM2 PERI1 PERI2 m 4K = 212 = $1000 4K = 212 = $1000 8K = 213 = $2000 2 = 21 = $0002 2 = 21 = $0002 m-1 $0FFF $0FFF $1FFF $0001 $0001

Device Memory Mapping

Device Name ROM1 RAM ROM2 PERI1 PERI2 Start Address $000000 $001000 $002000 $004000 $004002 End Address $000FFF $001FFF $003FFF $004001 $004003

Address Decoding Table

DEVICE ADDRESS LINE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ROM1 RAM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X

0 1 X X X

ROM2
PERI1 PERI2

0 0 0 0
0 0 0 0 0 0 0 0

0
0 0

0 0 0 0 0
0 0 0 0 1 0 0 0 0 1

1 X X
0 0 0 0 0 0

X X X X
0 0 0 0 0 0 0 0

X X
0 0 0 0

X X
0 0 0 0

X X
0 0 0 1

X
X X

Full Address Decoding Schematic Diagram Corresponding to Table

Partial address decoding

only a subset of the address lines are needed to point to the physical memory locations Each physical memory location is identified by several possible addresses

Example
Lets assume the same microprocessor with 10 address lines (1KB memory) However, this time we wish to implement only 512 bytes of memory We still must use 128-byte memory chips Physical memory must be placed on the upper half of the memory map

Solution

Partial Address Decoding

Memory Map

Address Decoding Table for Partial Address Decoding for Example

DEVICE ADDRESS LINE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 0 0 1 0 1 1 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

ROM1 RAM ROM2 PERI1 PERI2

X X X X

Partial Address Decoding for Example

Improved Partial Address Decoding Scheme

DEVICE A23 ROM1 0 A22 0 A21 0 A20 0

RAM ROM2 PERI1 PERI2 SPACE

0 0 0 0 1

0 0 1 1

0 1 0 1

Partial Address Decoding Schematic Diagram Corresponding to Table

Designing Address Decoders

Address Decoding with Random Logic Address Decoding with m-line-to-n-line Decoders Address Decoding with PROM Address Decoding with FPGA, PLA and PAL

m-line-to-n-line Decoders (e.g. 74LS138 Decoder)

Applications of the three-to-eight Decoder

Also, recall

Address Decoding with PROM

Used in place of random logic or a binary decoder Implements truth (look-up) table instead of Boolean logic m-bit address at its inputs selects one of 2m possible p-bit words capacity of the PROM required is p*2m

Advantages and Disadvantges

Advantages
able to select memory blocks of differing size
ROM1 and RAM1 are of different size

Versatile

Disadvantages
large PROM may be required for the decoding process depending on the values of p and m
making design and testing procedures complex

To solve the snag

Perform basic decoding with random logic Perform the finer decoding with PROM

An Example of Decoding with PROM

DEVICE

MEMORY SPACE (BYTES) 4K 4K 4K 2K 256 256 256

ADDRESS RANGE 000000 000FFF 001000 001FFF 002000 002FFF 00C000 00C7FF 00E000 00E0FF 00E100 00E1FF 00E200 00E2FF

ROM1 ROM2 ROM3 RAM1 PERI1 PERI2 PERI3

PROM-based Address Decoder Implementation

Programming of the Address Decoding PROM

Device Memory Space in Blocks

ROM1 ROM2 2 blocks 2 blocks 2 entries in PROM 2 entries in PROM

ROM3
RAM1 PERIs (decoder)

2 blocks
1 block

2 entries in PROM
1 entry in PROM

1 block (combined) 1 entry in PROM

System Address Lines Address range of A15 A14 A13 A12 A11 CPU PROM Address Input A4 A3 A2 A1 A0

System Device Enables PROM1 PROM2 PROM3 RAM1 PERIs PROM Data Output D7 D6 D5 D4 D3 D2 D1 D0

000000-0007FF 0
000800-000FFF 0 001000-0017FF 0 001800-001FFF 0 002000-0027FF 0 002800-002FFF 0 003000-0037FF 0 003800-003FFF 0 ----------

0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0
0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1

0
0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1

0
1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1

0
0 1 1 1 1 1 1 -do1 1 1 1 1 1 1 1 1

1
1 0 0 1 1 1 1 -do1 1 1 1 1 1 1 1 1

1
1 1 1 0 0 1 1 -do1 1 1 1 1 1 1 1 1

1
1 1 1 1 1 1 1 -do1 0 1 1 1 1 1 1 1

1
1 1 1 1 1 1 1 -do1 1 1 1 1 0 1 1 1

1
1 1 1 1 1 1 1

1
1 1 1 1 1 1 1

1
1 1 1 1 1 1 1

-do- -do- -do1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

00B800-00BFFF 1 00C000-00C7FF 1 00C800-00CFFF 1 00D000-00D7FF 1 00D800-00DFFF 1 00E000-00E7FF 1 00E800-00EFFF 00F000-00F7FF 00F800-00FFFF 1 1 1

Address Decoding with FPGA, PLA and PAL

Address decoding using general purpose programmable logic elements
the speed of random logic, and the flexibility of the PROM