Ece260b w05 Partition Floorplan

ECE 260B CSE 241A Partitioning & Floorplanning 1 http://vlsicad.ucsd.
edu
ECE260B CSE241A
Winter 2005

Partitioning & Floorplanning

Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B CSE 241A Partitioning & Floorplanning 2 http://vlsicad.ucsd.edu
Key Design Stages
Synthesis
Partitioning
Floorplanning
Power/ground Generation
Clock Generation
Placement
Routing

Floorplanning
Floorplanning Input
Design netlist (required)
Area requirements (required)
Power requirements (required)
Timing constraints (required)
Physical partitioning information (required)
Die size vs. performance vs. schedule trade-off (required)
I/O placement (optional)
Macro placement information (optional)
Floorplanning Output
Die/block area
I/Os placed
Macros placed
Power grid designed
Power pre-routing
Standard cell placement areas

Design ready for standard cell placement

Floorplanning Output
Floorplan
data path
RAM
std cell
blocks
I/O pads
Routing
channels
Blocks inside a pad
frame
Routing inside, between
blocks
Different-sized blocks
more difficult than
standard cells to place
and route
Blocks
Hard, soft, semi-soft
Rectangular, L-shaped,
T-shaped, rectilinear
Can rotate, mirror,
Courtesy K. Yang, UCLA
Design Styles
Full Customized
Analog / RF
CPU design
ASIC (Application Specific IC)
Gate array / sea of gate / standard cells
Via programmable
Structured ASICs
Programmable Logics
PLA
FPGA
Software implementation
Micro-code
Size Estimation
Why we care:
If area is too small: P&R will not finish or meet timing, will run too long
Schedule and die size inversely related
Performance and die size have complex relationship

Rule of thumb (must correct for power, clock, etc.):
- 3LM: Cell utilization 65 percent // what is utilization?
- 4LM: Cell utilization 70 percent
Floorplan metrics
Low interconnect density Cell util (standard cell area/standard cell row area)
High interconnect density Net util (number of nets/standard cell area)
Die size
Physical Design
Schedule Perf
Die size
Channels
Channels end at block boundaries
Alternate channel definitions
possible, depending on position of
blocks
A
B C
channel 1
ch 2
ch 1 ch 2
ch 3
A
B C
A
B
C
Channel Intersection Graph
Nodes are channels, edges correspond to pairs of
channels that touch
Channel graph shows paths between channels
Channel graph can be used to guide global routing
A
B
C
D
E
Channel Ordering
Wire out end of one channel
creates pin on side of next
channel

Wheel = Circular constraints
that create an unroutable
configuration of channels

channel A
channel B
constraint
A
B
C
D
Slicing Floorplan Represented by Binary Tree
A slicing floorplan can be
recursively cut in two without
cutting any blocks
A slicing floorplan is guaranteed to
have no wheels, therefore
guaranteed to have a feasible order
of routing for the channels
A slicing floorplan can be
represented as a binary tree, with
internal nodes representing slices
in the floorplan and leaves
representing blocks.

A
B
C
D
E
1
2
3
4
1
2 3
4
A B
C
D E
O-Tree
Partial ordering based on projection
overlapping (with given physical
locations)
Transforming into binary trees by
pivoting, etc.
Coded in a node sequence given a
tree traversal algorithm
E.g., OACBDEF for DFS
Condensed solution space
B
C
D
E
F
A
O
Sequence Pair
Based on layout partitions by non-
overlapping ascending/descending
staircases
Coded in two node sequences
E.g., CEDFAB for descending
staircases and
ABCDEF for ascending staircases
Larger solution space, finer
representation
B
C
D
E
F
A
Partitioning
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)
Partitioning
Decomposition of a complex system into smaller
subsystems
Done hierarchically
Partitioning done until each subsystem has manageable size
Each subsystem can be designed independently
Interconnections between partitions minimized
Less hassle interfacing the subsystems
Communication between subsystems usually costly
Time-budgeting

Example: Partitioning of a Circuit
Input size: 48
Cut 1=4
Size 1=15
Cut 2=4
Size 2=16

Size 3=17
Hierarchical Partitioning
Levels of partitioning:
System-level partitioning:
Each sub-system can be designed as a single PCB
Board-level partitioning:
Circuit assigned to a PCB is partitioned into sub-circuits
each fabricated as a VLSI chip
Chip-level partitioning:
Circuit assigned to the chip is divided into manageable sub-
circuits
NOTE: physically not necessary
Delay at Different Levels of Partitions
A
B
C
PCB1
D
x
10x
20x
PCB2
Partitioning: Formal Definition
Input:
Graph or hypergraph
Usually with vertex weights
Usually weighted edges
Constraints
Number of partitions (K-way partitioning)
Maximum capacity of each partition
OR
maximum allowable difference between partitions
Objective
Assign nodes to partitions subject to constraints
s.t. the cutsize is minimized
Tractability
Is NP-complete
Hypergraphs in VLSI CAD
Circuit netlist represented by hypergraph
Slides Courtesy Kia Bazargan, U. Minn
Hypergraph Partitioning in VLSI
Variants
directed/undirected hypergraphs
weighted/unweighted vertices, edges
constraints, objectives,
Human-designed instances
Benchmarks
up to 4,000,000 vertices
sparse (vertex degree 4, hyperedge size 4)
small number of very large hyperedges
Efficiency, flexibility: KL-FM style preferred
Some Notations
A net n is cut by a cluster C if at least one, but not all,
pins of n is in C.
We use E(C) to denote the set of nets cut by a cluster C.
We use E(P) to denote the set of nets cut by at least one
cluster of a partition P.
We use w(C) to denote the no. of cells assigned to a
cluster C.
Some Bipartitioning Formulations
Min-Cut Bipartitioning:
Objective : Minimize F(P
2
) = |E(C
1
)| = |E(C
2
)|
Min-Cut Bisection:
2
) = |E(C
1
)| = |E(C
2
)|
Constraint : |w(C
1
) - w(C
2
)| s c
Size-Constrained Min-Cut Bipartitioning:
2
) = |E(C
1
)| = |E(C
2
)|
Constraint: L s w(C
1
), w(C
2
) s U
Minimum Ratio Cut Bipartitioning:
Objective :
Minimize F(P
2
) = |E(C
1
)|/(w(C
1
)w(C
2
))
Some Multi-Way Partitioning Formulations
Size-Constrained Min-Cut k-Way Partitioning:
k
)
Constraint: L s w(C
i
) s U C
i
e P
k

Many other complicated formulations
k-way partitioning: Formulation

Given a netlist of n cells V = {v
1
, v
2
, , v
n
}, assign the
cells to k clusters P
k
= {C
1
, C
2
, , C
k
} satisfying some
given constraints such that an objective function F(P
k
) is
optimized.

Partitioning: k is small O(1)
Clustering: k is large O(n)
Technology Mapping: Constraints on the clusters
Outline
Introduction
Clustering
Kernighan-Lin (KL) Algorithm
On non-weighted graphs
An iterative improvement technique
A two-way (bisection) partitioning algorithm
The partitions must be balanced (of equal size)
Iterate as long as the cutsize improves:
Find a pair of vertices that result in the largest decrease in
cutsize if exchanged
Exchange the two vertices (potential move)
Lock the vertices
If no improvement possible, and
still some vertices unlocked, then
exchange vertices that result in smallest increase in cutsize
W. Kernighan and S. Lin, Bell System Technical Journal, 1970.
Kernighan-Lin (KL) Algorithm
Initialize
Bipartition G into V
1
and V
2
, s.t., |V
1
| = |V
2
| 1
n = |V|
Repeat
for i=1 to n/2
- Find a pair of unlocked vertices v
ai
e V
1
and v
bi
e V
2
whose
exchange makes the largest decrease or smallest increase
in cut-cost
- Mark v
ai
and v
bi
as locked
- Store the gain gi.
Find k, s.t. i=1..k g
i
=Gain k is maximized
If Gain k > 0 then
move v
a1
,...,v
ak
from V
1
to V
2
and
v
b1
,...,v
bk
from V
2
to V
1
.
Until Gain k s 0
An Example
a b c d
a
b
c
d
0 1 2 3
1 0 1 4
2 1 0 3
3 4 3 0
a
b d
c
1
2
3
1
4
3
Slides courtesy F. Y. Young, U. Hong Kong
An Example - Pass One
a
b d
c
1
2
3
1
4
3
g(a,c) = -1+3-3+1 = 0
g(a,d) = -1+2-3+4 = 2
g(b,c) = -1+4-3+2 = 2
g(b,d) = -1+1-3+3 = 0
g
1
= 2
d
b a
c
4
3
3
1
1
2
g(b,c) = -4+1-2+3 = -2
g
2
= -2
d
c a
b
3
4
3
1
2
1
G = g
1
= 2 (k = 1)
An Example - Pass Two
d
b a
c
4
3
3
1
1
2
g(a,b) = -2+3-4+1 = -2
g(a,d) = -2+1-4+3 = -2
g(c,b) = -2+3-4+1 = -2
g(c,d) = -2+1-4+3 = -2
g
1
= -2
b
g(a,b) = -3+2-1+4 = 2
g
2
= 2
G = g
1
+ g
2
= 0 (k = 2)
STOP!
a
d
c
1
3
4 2
3 1
d
c
a
b
1
3
3
1
4 2
Cut During One Pass (Bipartitioning)
Moves
Cut
Kernighan-Lin (KL) : Analysis
Time complexity?
Inner (for) loop
- Iterates n/2 times
- Iteration 1: (n/2) x (n/2)
- Iteration i: (n/2 i + 1) (n/2 i + 1).
Passes? Usually independent of n
O(n
3
)
Drawbacks?
Local optimum
Balanced partitions only
No weight for the vertices
High time complexity
Only on edges, not hyper-edges

Outline
Introduction
Clustering
Fiduccia-Mattheyses Algorithm: Basic Ideas
Differences from KL:
Move only one cell each time.
Cells can have different sizes.
Nets can be multi-terminal.
Maintain a balanced partition after every move.

FM Algorithm
Start with a balanced partition P = {X,Y}.
Repeat
For i = 1 to n:
- Choose a free cell b e XY s.t. moving b to the other side gives the
highest gain, gain(b), and moving b preserves balance in P.
- Move and lock b.
- Let gi = gain(b).
Find k s.t. G = g1 + g2 + .. + gk is maximized and shuffle the
cells up to this kth step.
Until G = 0.
An Example
a
b
c
d
e
f
a
c
d
e
f
b
locked
a
c
d
f
b e
a
c
f
b
e
d
g
1

g
2

g
3

g
4

An Example
c
f
b
e
d
g
5

a
f
b
e
d
g
6

a
c
b
e
d
a
c f
If G = g
1
+ g
2
+ g
3
+ g
4
is the largest partial sum,
the partition after this pass is:
c
d
e
a
f
b
Balanced Partition
A partition P = (X,Y) is balanced iff:

for some constant r s 1 where w(X) is the total size of the
cells in X. To preserve balance, a cell b is moved in a
pass only if:

after moving b where W = w(XY) and Smax is the
maximum cell size
r
Y X
X
~
) ( w
) ( w
max max ) ( S rW X w S rW + s s
KL and FM Extensions: Tie-Breaking Strategy
When picking the highest gain move, break ties by
looking ahead a certain number of steps.
If ties still occur, some researchers observe that LIFO
order improves solution quality.
Ratio of #edges to #vertices
Solution quality of KL and FM depends on the ratio of
#edges to #vertices: good if ratio > 5 and bad if ratio < 3.
VLSI circuits have ratio 1.8-2.5 typically.
Goldberg and Burstein suggested contracting edges to
increase the ratio:
A B AB
Outline
Introduction
Clustering
Network Flow Technique
s t
a
b
c d
16
13
10 4 9 7
12
20
4
11
s t
a
b
c d
11/16
12/13
10 1/4 9 7/7
12/12
19/20
4/4
11/11
min-cut = max-flow
The network flow technique can find the min-cut
bipartition optimally, but not necessarily balanced.
Apply the algorithm repeatedly to obtain a balanced
bipartition.
Network Flow Technique
The network flow technique is very useful in many
different research areas.
Many sophisticated improvements have been made to
the original algorithm.
Ford & Fulkerson: O(|E||f|) where |f| is the size of the
total flow. Note that for unit capacity, |f| s |E|, so O(|E|
2
)
time.
Circuit Partitioning
We can apply the network flow algorithm in partitioning
circuits.
The biggest problem is that the two partitions may not be
balanced.
The problem of obtaining two balanced partitions with
minimum cut is NP-complete.
However we can apply some heuristics to balance the
two partitions.
Flow-Balanced-Bipartition (FBB)
Find a min-cut C = (X,Y) in the network N
If (1-c)W/2 s w(X) s (1+c)W/2, stop and return C
If w(X) < (1-c)W/2 then
Collapse all nodes in X to s
Collapse to s a node veY incident on a net in C
Go to to step 1
If w(X) > (1+c)W/2 (similarly) ...
Why do we need
this step?
Circuit Representation
Another problem in applying the network flow technique
in circuit partitioning is how to represent a circuit correctly
by a graph.
A B C D
How to represent this netlist by a simple graph?
Hypergraph
A B C D
H(V,E) where
V = {A, B, C, D}
E = {n
1
, n
2
, n
3
}
n
1
= {A, B, C, D}
n
2
= {A, B}
n
3
= {C, D}
In hypergraph, an edge is a set of vertices.
Circuits can be represented by hypergraphs, but the net-
work flow method can only be used in simple graphs.
Weighted Undirected Graph
Use a clique to model a net:
A B C D
What should be the edge weights?
A proper model for the partitioning of electrical circuits,
Schweikert and Kernighan, DAC, 1972.
A B C D
1/4
1/4 1/4
1/4 1/4 1/4
1/2 1/2
Cut size = 4*1/4
= 1 (Actual cut size = 1)
Cut size = 3*1/4+1/2 = 5/4
(Actual cut size = 2)
edge weight =
n(k) = no. of cells
in net k
n(i)
1
A B C D
1/3
1/3 1/3
1/3 1/3 1/3
1 1
Cut size = 4*1/3
= 4/3 (Actual cut size = 1)
Cut size = 3*1/3+1 = 2
(Actual cut size = 2)
edge weight =
1 ) (
1
i n
Circuit Representation
It is proved that exact modeling of a hypergraph by a
graph with positive weights is impossible. [Ihler, Wagner
& Wager, 1993]
However, we can model a hypergraph H by a simple
graph G such that when we apply the network flow
algorithm, the min-cut in G is equal to the min-cut in H.

Weighted Directed Graph
A
B
C
A
B
C

1
What will happen when we apply the max-flow min-cut
algorithm to the graph G?
Original circuit C:
G:
Weighted Directed Graph
A B C D

1

1

1
Modeling a Circuit
d
a
b
c
e
f
g
d
s
b
c
e
f
t
C: G:
Modeling a Circuit
Lemma: If C has a cut (X,Y) of size K, G has a cut (X,Y) of
size K. If G has a cut (X,Y) of size K, C has a cut (X,Y) of
size less than or equal to K
Corollary: If (X,Y) is the min-cut of G of size K, the
corresponding cut (X,Y) in C is also a min-cut of C of size K
Let G = (V,E) be the flow network modeling the circuit C =
(V,E):

A
B
C

1
C: G:
A
B
C
|V| = ?
|E| = ?

Efficient Implementation
Repeatedly computing max-flow is time consuming. No
need to compute max-flow from scratch in every
iteration.
Retain the flow function computed in the previous
iteration. Find additional flow to saturate the bridging
edges from one iteration to another.

Total time taken for all the iterations is O(|E||V|).
Outline
Introduction
Clustering
Clustering
Clustering
Bottom-up process
Merge heavily connected components
into clusters
Each cluster will be a new node
Hide internal connections (i.e.,
connecting nodes within a cluster)
Merge two edges incident to an
external vertex, connecting it to two
nodes in a cluster
Can be a preprocessing step before
partitioning
Each cluster treated as a single node
3
4
1 6
2 5
6
4
3
1
1
1
3
4
6
1,2
5
4
3
1
2
3,4
6
1,2
5
3
1
2
Ratio Cut Objective
It is not desirable to have a pre-defined ratio on the
partition sizes.
Wei and Cheng proposed the ratio cut objective (
C
XY
/(|X||Y|) where C
XY
is the cut size ). Try to locate
natural clusters in the circuit.
A heuristic based on FM was proposed.
Multi-Level Partitioning
Clustering
Clustering
Clustering
Applying FM
Unclustering
Unclustering
Unclustering
Refining by FM
hMETIS
Freely available at
http://www-users.cs.umn.edu/~karypis/metis/hmetis/
Extension of METIS graph hierarchical partitioning tool
Coarsening phase
Refinement phase
See also UCLA MLPart
http://vlsicad.ucsd.edu/GSRC/Slots/Partitioning/MLPart/

initial
hypergraph
projected
partition
refined
partition
random
partition
Coarsening
Goal: create a smaller hypergraph such that a good
bisection is not significantly than one on the original
How to select the vertices to condense?
edge coarsening
- best matching pairs of hyperedge vertices are collapsed
hyperedge coarsening
- independent set of hyperedges are collapsed
- preference given to maximum weights and small sizes
modified hyperedge coarsening
- hyperedge coarsening followed by collapse of the remaining
vertices that do not belong to another hyperedge
Coarsening (contd)
edge coarsening hyperedge coarsening
modified hyperedge
coarsening
3 hyperedges
12 vertices
5.3 pins / hyperedge
3 hyperedges
6 vertices
3.3 pins / hyperedge
1 hyperedge
5 vertices
5 pins / hyperedge
1 hyperedge
3 vertices
3 pins / hyperedge
Uncoarsening
Initial partition is a balanced random bisection
Partition is refined at this level
Fiduccia-Mattheyses (FM-EE)
- constrained to only two passes
- each pass is stopped after k zero-gain moves (early-exit)
- Hyperedge Refinement (HER)
entire hyperedges are moved across the cut

Projection of cut onto more complete hypergraph

Outline
Introduction
Clustering

Ece260b w05 Partition Floorplan

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ECE 260B CSE 241A Partitioning & Floorplanning 1 http://vlsicad.ucsd.

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