S11 Bus Interface

Chapter 15: Bus Interface
Introduction
This chapter presents the ISA (industry standard architecture) bus, the PCI (peripheral component interconnect) and PCI Express buses, the USB (universal serial bus), and the AGP (advanced graphics port). Also provided are some simple interfaces to many of these bus systems as design guides.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions
Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey
Copyright 2009 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
151 The ISA BUS

The Industry Standard Architecture, bus has been around since start of the IBM-PC
circa 1982
Any card from the very first personal computer will plug in & function in any P4-based system.
provided they have an ISA slot
ISA bus mostly gone from the home PC, but still found in many industrial applications.
due to low cost & number of existing cards
Evolution of the ISA Bus

Over years, the ISA bus evolved from original 8-bit, to the 16-bit standard found today. With the P4, ISA bus started to disappear.
a 32-bit version called the EISA bus (Extended ISA) has also largely disappeared
What remains today is an ISA slot that can accept 8-bit ISA or 16-bit ISA cards. 32-bit printed circuit cards are now PCI bus
in some older 80486 systems, VESA cards
The 8-Bit ISA Bus Output Interface

Fig 151 shows an 8-bit ISA connector as found on the main board of all PC systems
may be combined with a 16-bit connector
The ISA bus connector contains

the demultiplexed address bus (A19A0) for the 1M-byte 8088 system the 8-bit data bus (D7D0) control signals MEMR, MEMW, IOR, and IOW for controlling I/O and any memory placed on the printed circuit card
Memory is seldom added to ISA today because ISA cards operate at only 8 MHz.
EPROM or flash memory for setup may be on some ISA cards, but never RAM
Other signals, useful for I/O interface, are the interrupt request lines IRQ2IRQ7. DMA channel 03 control signals are also present on the connector. DMA request inputs are labeled DRQ1 DRQ3 and the DMA acknowledge outputs are labeled DACK0 - DACK3.
Figure 151 The 8-bit ISA bus.
IRQ2 is redirected to IRQ9 on modern systems, and is so labeled here note the DRQ0 input pin is missing, early PCs used DRQ0 & the DACK0 output as a refresh signal to refresh DRAM on the ISA card today, this output pin contains a 15.2 s clock signal used for refreshing DRAM remaining pins are for power and RESET
Fig 152 shows an interface for the ISA bus, which provides 32 bits of parallel TTL data.
this example system shows some important points about any system interface
It is extremely important that loading to the bus be kept to one low-power (LS) TTL load.
a 74LS244 buffer reduces loading on the bus
If all bus cards were to present heavy loads, the system would not operate properly.
perhaps not at all

Figure 152 A 32-bit parallel port interfaced to the 8-bit ISA bus.

In the PC, the ISA bus is designed to operate at I/O address 0000H through 03FFH. Newer systems often allow ISA ports above 03FFH, but older systems do not.
some older cards only decode 0000H03FFH & may conflict with addresses above 03FFH
The ports in 152 are decoded by three 74LS138 decoders.

more efficient and cost-effective to decode the ports with a programmable logic device

10
The 8-Bit ISA Bus Input Interface

Figure 154 shows an input interface to the ISA bus, using a pair of ADC804 analog-todigital converters.
made through a nine-pin DB9 connector
Decoding I/O port addresses is more complex, as each converter needs:

a write pulse to start a conversion a read pulse to read the digital data converted a pulse to enable the selection of the INTR output
11
Figure 154 A pair of analog-to-digital converters interfaced to the ISA bus.

12
The 16-Bit ISA Bus

The difference between 8- & 16-bit ISA is an extra connector behind the 8-bit connector. A 16-bit card contains two edge connectors:
one plugs into the original 8-bit connector the other plugs into the new 16-bit connector
Figure 155 shows pin-out and placement of the additional connector in relation to the 8-bit connector.

13
Figure 155 The 16-bit ISA bus. (a) Both 8- and 16-bit connectors and (b) the pinout of the 16-bit connector.

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152 PERIPHERAL COMPONENT INTERCONNECT (PCI) BUS

PCI (peripheral component interconnect) is virtually the only bus found in new systems.
ISA still exists by special order for older cards
PCI has replaced the VESA local bus. PCI has plug-and-play characteristics and ability to function with a 64-bit data bus.

15
A PCI interface contains registers, located in a small memory device containing information about the board.
this allows PC to automatically configure the card this provides plug-and-play characteristics to the ISA bus, or any other bus
Called plug-and-play (PnP), it is the reason PCI has become so popular. Figure 156 shows the system structure for the PCI bus in a PC system.
16
Figure 156 System block diagram for the PC that contains a PCI bus.
the microprocessor connects to the PCI bus through an IC called a PCI bridge
virtually any processor can interface to PCI with a bridge The resident local bus is often called a front side bus
17
The PCI Bus Pin-Out

PCI functions with a 32- or 64-bit data bus and a full 32-bit address bus.
address and data buses, labeled AD0AD63 are multiplexed to reduce size of the edge connector
A 32-bit card has connections 1 through 62, the 64-bit card has all 94 connections. The 64-bit card can accommodate a 64-bit address if required at some future point. Figure 157 shows the PCI bus pin-out.
18
Figure 157 The pin-out of the PCI bus.
PCI is most often used for I./O interface to the microprocessor memory could be interfaced, but with a Pentium, would operate at 33 MHz, half the speed of the Pentium resident local PCI 2.1 operates at 66 MHz, and 33 MHz for older interface cards P4 systems use 200 MHz bus speed (often listed as 800 MHz) there is no planned modification to the PCI bus speed yet
19
The PCI Address/Data Connections

The PCI address appears on AD0AD31 and is multiplexed with data.
some systems have a 64-bit data bus using AD32AD63 for data transfer only these pins can be used for extending the address to 64 bits
Fig158 shows the PCI bus timing diagram

which shows the address multiplexed with data and control signals used for multiplexing

20
Figure 158 The basic burst mode timing for the PCI bus system. Note that this transfers either four 32-bit numbers (32-bit PCI) or four 64-bit numbers (64-bit PCI).

21
Configuration Space
PCI contains a 256-byte memory to allow the PC to interrogate the PCI interface.
this feature allows the system to automatically configure itself for the PCI plug-board Microsoft calls this plug-and-play (PnP)
The first 64 bytes contain information about the PCI interface. The first 32-bit doubleword contains the unit ID code and the vendor ID code. Fig159 shows the configuration memory.
22
Figure 159 The contents of the configuration memory on a PCI expansion board.

23
Unit ID code is a 16-bit number (D31D16).

a number between 0000H & FFFEH to identify the unit if it is installed FFFFH if the unit is not installed
The class code is found in bits D31D16 of configuration memory at location 08H.
class codes identify the PCI interface class bits D15D0 are defined by the manufacturer
Current class codes are listed in Table 155 and are assigned by the PCI SIG.
24
The base address space consists of a base address for the memory, a second for the I/O space, and a third for the expansion ROM. Though Intel microprocessors use a 16-bit I/O address, there is room for expanding to 32 bits addressing. The status word is loaded in bits D31D16 of location 04H of the configuration memory.
the command is at bits D15D0 of 04H
Fig 1510 shows the status & command registers.

25
Figure 1510 The contents of the status and control words in the configuration memory.

26
BIOS for PCI

Most modern PCs have an extension to the normal system BIOS that supports PCI bus.
these systems access PCI at interrupt vector 1AH
Table 156 lists functions available through the DOS INT 1AH instruction with AH = 0B1H for the PCI. Example 155 shows how the BIOS is used to determine whether the PCI bus extension available.
27
PCl Interface
If a PCI interface is constructed, a PCI controller is often used because of the complexity of this interface. The basic structure of the PCI interface is illustrated in Figure 1511.
the diagram illustrates required components for a functioning PCI interface
Registers, Parity Block, Initiator, Target, and Vendor ID EPROM are required components of any PCI interface.
28
Figure 1511 The block diagram of the PCI interface.

29
PCI Express Bus

The PCI Express transfers data in serial at 2.5 GHz to legacy PCI applications,
250 MBps to 8 GBps for PCI Express interfaces standard PCI delivers data at about 133 MBps
Each serial connection on the PCI Express bus is called a lane.

slots on the main board are single lane slots with a total transfer speed of 1 GBps
A PCI Express video card connector currently has 16 lanes with a transfer speed of 4 GBps.
30
The standard allows up to 32 lanes.

at present the widest is the 16 lanes video card
Most main boards contain four single lane slots for peripherals and one 16 lane slot for the video card.
a few newer boards contain two 16 lane slots
PCI Express 2 bus was released in late 2007.

transfer speed from 250 MBps to 500 MBps, twice that of the PCI Express
PCI is replacing most current video cards on the AGP port with the PCI Express bus.
31
This technology allows manufacturers to use less space on the main board and reduce the cost of manufacturing a main board.
connectors are smaller, which also reduces cost
Software used with PCI Express remains the same as used with the PCI bus.
new programs are not needed to develop drivers
The connector is a 36-pin connector as illustrated in Figure 1512.

32
the pin-out for the single lane connector, appears in Table 157 signaling on the PCI Express bus uses 3.3 V with differential signals degrees out of phase the lane is constructed from a pair of data pipes, one for input data and one for output data
Figure 1512 The single lane PCI Express connector.

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153 THE PARALLEL PRINTER INTERFACE (LPT)

The parallel printer interface (LPT) is located on the rear of the PC. LPT stands for line printer. The printer interface gives the user access to eight lines that can be programmed to receive or send parallel data.

34
Port Details
The parallel port (LPT1) is normally at I/O addresses 378H, 379H, & 37AH from DOS.
or by using a driver in Windows
The secondary (LPT2) port, if present, is located at 278H, 279H, & 27AH. The connectors are shown in Figure 1513.

35
Figure 1513 The connectors used for the parallel port.
the Centronics interface on the parallel port uses two connectors a 25-pin D-type on the back of the PC a 36-pin Centronics on the back of the printer the pin-outs of these connectors are listed in Table 158
36
The parallel port can work as both a receiver and a transmitter at its data pins (D0D7).
allows other devices such as CD-ROMs, to be connected to and used by the PC through port
Anything that can receive and/or send data through an 8-bit interface can and often does connect to the parallel port (LPT1) of a PC. See Figure 1514.

37
Figure 1514 Ports 378H, 379H, and 37AH as used by the parallel port.
Shown here are the contents of:

the data port (378H) the status register (379H) an additional status port (37AH) note that some of the status bits are true when logic 0
38
Using the Parallel Port Without ECP Support

For most systems since the PS/2, one can follow the information presented in Fig 1514 to use the parallel port without ECP. To read the port, it must be initialized by sending 20H to register 37AH. See Ex 156. This sets the bidirectional bit to selects input operation for the parallel port.
if the bit is cleared, output operation is selected
39
On 80286 systems, the bidirectional bit is missing from the interface.

these systems do not have a register at 37AH to read information from the parallel port, write 0FFH to the port (378H), so that it can be read
Accessing the printer port from Windows is difficult because a driver must be written for Windows 2000 or Windows XP. Windows 98 or Windows ME port access is accomplished as explained for DOS.
40
A driver called UserPort (available on the Internet) opens up protected I/O ports in Windows 2000 & XP without using a driver. This allows direct access to the parallel port through assembly blocks in Visual C++ using I/O port address 378H.
also access to ports between 0000H & 03FFH
Another useful tool is available for a 30-day trial at http://www.jungo.com.

41
154 THE SERIAL COM PORTS

Serial communications ports are COM1COM8
most PCs have only COM1 and COM2 installed
Under DOS these ports are controlled and accessed with the 16550 serial interface. Windows API functions operate the COM ports for the 16550 communications interface. USB devices often interface using the HID (human interface device) as a COM port.
allows standard serial software to access USB
42
Communication Control
An example of a C++ function to access serial ports is listed in Example 159. It is called WriteComPort, and it contains two parameters:
first parameter is the port, as in COM1, COM2 second is the character to send through the port
A return true indicates the character was sent.

return false indicates a problem exists

43
To send the letter A through the COM1 port call it with a WriteComPort (COM1, A). This function is written to send only a single byte through the serial COM port.
but could be modified to send strings
To send 00H (no other number can be sent this way) through COM2 use WriteComPort (COM2, 0x00). Note the COM port is set to 9600 baud.
easily changed by changing the CBR_9600 to another acceptable value
44
Receiving data is more challenging as errors occur more frequently than with transmission.
many types of errors can be detected that often should be reported to the user
Example 1510 shows a C++ function called ReadByte, which returns the character read from the port.
or error code 0100 if the port couldnt be opened or 0101 if the receiver detected an error
If data are not received, the function will hang because no timeouts were set.
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155 THE UNIVERSAL SERIAL BUS

The universal serial bus (USB) has solved a problem with the PC system. Current PCI sound cards use internal PC power, which generates a lot of noise.
USB allows the sound card to have its own power supply, for high-fidelity sound with no 60 Hz hum
Other benefits are ease of connection and access to up to 127 different connections. The interface is ideal for keyboards, sound cards, simple video-retrieval, and modems.
46
Data transfer speeds are 480 Mbps for fullspeed USB 2.0 operation.
11 Mbps for USB 1.1 compliant transfers 1.5 Mbps for slow-speed operation
Cable lengths are limited to five meters for the full-speed interface and three meters maximum for the low-speed interface. Maximum power through the cables is rated at 100 mA, maximum current at 5.0 V.
if current exceeds 100 mA, Windows will indicate an overload condition
47
The Connector
two types of connectors are specified, both are in use there are four pins on each connector, with signals indicated in Table 1510 the +5.0 V and ground can power devices connected to the bus data signals are biphase signals when +data are at 5.0 V, data are at zero volts and vice versa
Figure 1515 The front view of the two common types of USB connectors.
48
USB Data
Data signals are biphase signals generated using a circuit such as shown in Fig 1516. The line receiver is also shown. A noise-suppression circuit available from Texas Instruments (SN75240) is placed on the transmission pair Once the transceiver is in place, interfacing to the USB is complete.

49
a 75773 IC from Texas Instruments functions as differential line driver and receiver here
Figure 1516 The interface to the USB using a pair of CMOS buffers.
50
USB uses NRZI (non-return to zero, inverted) encoding to transmit packet data this method does not change signal level for the transmission of logic 1 signal level is inverted for each change to logic 0
Figure 1517 NRZI encoding used with the USB.

51
Actual data transmitted includes sync bits, a method called bit stuffing, because it lengthens the data stream. If logic 1 is transmitted for more than 6 bits in a row, the bit stuffing technique adds an extra bit (logic 0) after six continuous 1s in a row. Bit stuffing ensures the receiver can maintain synchronization for long strings of 1s.
data are always transmitted with the leastsignificant bit first, followed by subsequent bits
See Fig 1518.

52
Figure 1518 The data stream and the flowchart used to generate USB data.
a bit-stuffed serial data stream and the algorithm used to create it from raw digital serial data

53
USB Commands
To begin communication, sync byte 80H is transmitted first, followed by the packet identification byte (PID). The PID contains 8 bits.
only the rightmost 4 bits contain the type of packet that follows, if any
The leftmost 4 bits of the PID are the ones complementing the rightmost 4 bits.

54
Figure 1519 lists formats of data, token, handshaking, and start-of-frame packets.
in the token packet, the ADDR (address field) contains the 7-bit address of the USB device up to 127 devices present on at a time
ENDP (endpoint) is a 4-bit number used by the USB.

Endpoint 0000 is used for initialization other endpoints are unique to each USB device

55
Figure 1519 The types of packets and contents found on the USB.

56
Two types of CRC (cyclic redundancy checks) used on USB.

5-bit CRC generated with polynomial X5 + X2 + 1 a 16-bit CRC, used for data packets, generated with the X16 + X15 + X2 + 1 polynomial
When using 5-bit CRC, a residual of 01100 is received for no error in all five bits of the CRC and the data bits.
a 16-bit no error CRC residual is 1000000000001101

57
Once a packet is transferred from host to USB device, if data & CRC are received correctly, ACK (acknowledge) is sent to the host. If data and CRC are not received correctly, the NAK (not acknowledge) is sent.
if the host receives a NAK token, it retransmits the data packet until it is received correctly
This method of data transfer is often called stop and wait flow control.
host must wait for client to send an ACK or NAK before transferring additional data packets
58
The USB Bus Node

National Semiconductor produces a USB bus interface easy to interface to the processor. Connect this device using non-DMA access:
connect the data bus to D0D7 connect control inputs RD, WR, and CS and a 24 MHz fundamental crystal across XIn and XOut pins
The USB bus connection is located on the D and D+ pins. Figure 1520 shows a USBN9604 USB node.
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Figure 1520 The USB bus node from National Semiconductor.
USBN9604 is a USB bus transceiver that can receive and transmit USB data this provides an interface point to the USB bus for a minimal cost of about two dollars

60
Simplest interface is achieved by connecting the two mode inputs to ground. This places the device into nonmultiplexed parallel mode.
in this mode the A0 pin is used to select address (1) or data (0)
Fig 1521 shows this connection decodes at I/O addresses 0300H (data) and 0301H (address)

61
Figure 1521 The USBN9604 interfaced to a microprocessor at I/O addresses 300H and 301H.

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156 ACCELERATED GRAPHICS PORT (AGP)

The latest addition to most systems was the accelerated graphics port (AGP), until PCI Express became available for video. It is designed for transfer between video card and system memory at a maximum speed.
AGP transfers at a maximum of 2G bytes/sec

63
The main advantage of AGP over PCI bus is AGP can sustain transfers at speeds up to 2G bytes per second. (8X compliant system).
4X system transfer rate is over 1G byte/sec
AGP is designed to allow high-speed transfer between the video card frame buffer and system memory through the chip set. Fig 1522 shows interface of the AGP to a Pentium 4 system
and placement of other buses in the system

64
Figure 1522 Structure of a modern computer, illustrating all the buses.

65

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Chapter 15: Bus Interface

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

151 The ISA BUS

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Evolution of the ISA Bus

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The 8-Bit ISA Bus Output Interface

The ISA bus connector contains

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Figure 151 The 8-bit ISA bus.

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The ports in 152 are decoded by three 74LS138 decoders.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The 8-Bit ISA Bus Input Interface

Decoding I/O port addresses is more complex, as each converter needs:

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Figure 154 A pair of analog-to-digital converters interfaced to the ISA bus.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The 16-Bit ISA Bus

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

152 PERIPHERAL COMPONENT INTERCONNECT (PCI) BUS

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The PCI Bus Pin-Out

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Figure 157 The pin-out of the PCI bus.

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The PCI Address/Data Connections

Fig158 shows the PCI bus timing diagram

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Unit ID code is a 16-bit number (D31D16).

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Fig 1510 shows the status & command registers.

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

BIOS for PCI

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

Figure 1511 The block diagram of the PCI interface.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Architecture, Programming, and Interfacing, Eighth Edition Barry B. Brey

PCI Express Bus

Each serial connection on the PCI Express bus is called a lane.