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# Lecture 8 (Chap 6-3)

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## artificial vs. natural, or order vs. disorder

guests uninvited
gate leakage subthreshold leakage

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Tunneling current thru gate insulator 1. exponential dependence on thickness 2. Smaller for PMOS (tunneling barrier is lower for hole.)

Neither VDD reduction nor temperature lowering significantly decreases gate leakage. Insulator thickness and dielectric constant mainly counts.

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As T rises, Vth decreases, and mobility decreases. Gate turns in its current control to temperature.

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We say its due to mobility decrease. What is mobility, then? Velocity is more physical. Lets think & talk about velocity (Mobility is a phenomenal variable.) Velocity depends heavily on temperature. What is temperature, then?

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## heat : temperature = charge : voltage?

Heat denotes amount of vibration
Charge is number of excess electrons
Excess electron =? Free electron

## HW #2 (due one week, 3/20)

Study into the analogy and difference between charge and heat, voltage and temperature, electrical conductivity and thermal conductivity, capacitance and specific heat.

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CMOS idea is like a happy marriage between NMOS and PMOS, electron and hole

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## Noise margin static NM < dynamic NM

PMOS threshold voltage, Transconductance ratio

R-ratio

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## Compromise between static performance (VOL) and dynamic performance(rise time)

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In pseudo NMOS p=8 for I/3 for PMOS and (4/3)I for NMOS

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## Unit transmission gate vs. 2:1 ratioed transmission gate (4/5)R R

Ex. Compare the RC product between 2:1 ratioed transmission gate and unit transmission gate

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## (b) (without blue taps) can be obtained in two ways.

1. From (a), by disconnecting sources of PMOS and NMOS 2. From ~y=~(SA+~SB)=~(SA)~(~SB)=

(~S+~A)(S+~B)=~S~B+S~A+~A~B=
~S~B+S~A+~A~B(S+~S)= ~S~B+S~A

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With blue taps in, width ratio bet. Pmos and Nmos is 1:1, and 2:1 without blue taps. CMOS TG by itself is laid out in 1:1 width ratio, while CMOS TG with other transistors like this case can be laid out in 2:1width ratio.

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Y=SA+~SB or ~Y=~(SA+~SB) (a) CPL(Complementary Pass Tr. Logic) (b) inverter relocated (c) inverter redrawn in Tr. Level -> becomes CV if weak pullup PMOSs are omitted.

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## Circuit Pitfalls ; why chips fail

Threshold drops Ratio failures Leakage Charge sharing

Coupling

## Minority carrier injection

Back gate coupling

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## Circuit Pitfalls ; why chips fail

Diffusion input noise sensitivity Race conditions Delay matching Hot spots

Soft errors
Process sensitivity

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Ratio failure

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## Guard ring like a ditch around your tent on a rainy night

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Back gate coupling : Dynamic gate vulnerable with its high output impedance can be attacked by other inputs of the next stage.

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## Compare between static gate and dynamic gate

Static gate
Noise margin Output impedance area Directionality speed Good (high) Good (low) Bad (large) best Bad (slow)

Dynamic gate
Bad (low) Bad (high) Good (small) medium Good (fast)

## Pass tr logic gate

Worst (w/o input buffer) Worst (w/o output buffer) Best worst slowest Medium/bad

Noise immunity

Good
best