Verilog Day

Delay Models Path Delays VCD Files FSM Coding Styles Synthesis Issues

Types of delay models

Distributed delays:Assigning delay values to individual elements Lumped delays:single delay on the output gate of module Pin to Pin delays:Assigned individually to paths i.e .,each input to each output

Distributed and lumped delays

Distributed delay assign #2 x=a & b; assign #5 y=c & d; assign #10 z=x & y; Lumped delays assign x=a & b; assign y=c & d; assign #17 z=x & y;

Pin to Pin delay

Specify block:Block in which path delay are assigned syntax specify assignments . endspecify

Specify block
Within specify block path delays can be assigned in either of the two statements Parallel connection (<source field> => <destination filed>)=<delay_value > Example : (a=> out)=5; Full connection (<source field>*> <destination field>)=<delay_value> Example (a*> out) =5;

Specify block
Parallel connection Each bit in source field connects to corresponding bit in destination field Full connection Each bit in source field connects to every bit in destination field

Pin to Pin Delays

Full connections

Specparam
To declare parameters inside the specify block Keyword-specparam Example specify specparam a=15;specparam b=10; (in1=>out)=a; (in2=>out)=b; endspecify

Timing Checks

$setup Task
Setup checks can be specified with the system task $setup. Syntax: $setup(data_event, reference_event, limit) data_event: signal that is monitored for violations. reference_event: signal that establishes a reference for monitoring the data_event signal. limit: minimum time required for setup of data event.

 Violation is reported if(Treference_eventTdata_event)< limit. E.g. //setup check is set. // clock is the reference. //data is begin checked for violations // violation reported if Tposedge_clk-Tdata<3 Specify $setup(data,posedge clk,3); endspecify

 module set(d,q,clk); input d,clk; output q; reg q; always@(posedge clk) begin q=d; end specify $setup(d,posedge clk,5); endspecify endmodule

 Hold checks can be specified with the system task $hold. Syntax: $hold(reference_event, data_event,limit) data_event: signal that is monitored for violations. reference_event: signal that establishes a reference for monitoring the data_event signal. limit: minimum time required for hold of data event.

 Violation is reported if(Tdata_eventTreference_event)< limit. E.g. //hold check is set. // clock is the reference. //data is begin checked for violations // violation reported if Tdata-Tposedge_clk<3 Specify $hold(posedge clk, data,3); endspecify

 module hold(d,q,clk); input d,clk; output q; reg q; always@(posedge clk) begin q=d; end specify $hold(posedge clk,d,5); endspecify endmodule

$pulse Width
The system task $width is used to check that the width of a pulse meets the minimum width requirement. Syntax: $width(reference_event,limit); reference_event: edge trigger event(edge transistion of a signal). limit: minimum width of the pulse.

 The data event is not specified explicitly for width but is defined as the next opposite edge of the reference_event signal. Thus, the width task checks the time b/w the transition of a signal value to the next opposite transition in the signal value.

 Violation is reported if(Tdata_eventTreference_event)< limit. E.g. //width check is set. // posedge of clear is the reference_event. // the next negedge of clear is the data_event. // violation reported if Tdata-Tclk<6 Specify $width(posedge clk, 6); endspecify

 module width(d,q,clk); input d,clk; output q; reg q; specify $width(posedge d,9); endspecify endmodule

Delay Back Annotation

RTL Level Description

Logic Synthesis Initial Pre-Layout Delay Estimate Delay value Gate-Level Netlist

Back-annotation of Post-layout Delay delay Calculation

Postlayout inform ation

Place and Route

Layout

Implementation

Delay back annotation is an important and vast topic in timing simulation The various steps In the flow that use back annotation are as follows 1. The designer writes the RTL description and then performs functional simulation. 2. The RTL description is converted to a gate-level netlist by a logic synthesis tool.

3. The designer obtains pre-layout estimator of delays in the chip by using a delay calculator and information about the IC fabrication process. Then the designer does timing simulation or static timing verification of the gate level netlist, using these preliminary values to check that the gate level netlist meets timing constraints.

4 . The gate level netlist is then converted to layout by a place and route tool. The post-layout delay values are computed from the resistance and capacitance information in the layout. The R and C information is extracted from factors such as geometry and IC fabrication process. 5. The post-layout delay values are back annotated to modify the delay estimates from the gate level netlist.

 Timing simulation or static timing. verification is run again on the gate level netlist to check if timing constraints are still satisfied. 6. If design changes are required to meet the timing constraints, the designer has to go back to the RTL level, optimize the design for timing, and then repeat step2 through step 5.