UDP (User Defined Primitive)

Parts Of UDP Definition

//UDP name and terminal list

Primitive<UDP_name>( <output_terminal_name>(only one allowed) <input_terminal_name>);

//Terminal declarations

output<output_terminal_name>; input<input_terminal_name>; reg<output_terminal_name>;(optional;only for sequential UDP)

//UDP initialization(optional;only for sequential UDP

Initial <output_terminal_name>=<value>;
//UDP state table

table
<table entries>

endtable
//end of UDP defination

UDP RULES
1. UDPs can take only scalar input terminals(1 bit). Multiple input terminal are permitted. 2. UDPs can have only one scalar output terminal(1 bit). The output terminal must always appear first in the terminal list. Multiple output terminals are not allowed. 3. In the declaration section, the output terminal is declared with the keyword output. Since sequential UDPs store state, the output terminal must also be declared as a reg. 4. The inputs are declared with the keyword input.

5. The state in a sequential UDP can be initialized with an initial statement. This statements is optional. A 1 bit value is assigned to the output, which is declared as a reg. 6.The state table entries can contain values 0,1, or x. UDPs do not handle z values passed to a UDP are treated as x values. 7. UDPs are defined at the same level as modules. UDPs cannot be defined inside modules. They can be instantiated only inside modules. UDPs are instantiated exactly like gate primitives. 8. UDPs do not support inout ports

Combinational UDps
Combinational UDPs takes the inputs and produce the output value by looking up the corresponding entry in the state table. Combinational UDP definition :The satte table is the most important part of the UDP definition. E.g. and gate primitive and call it UDP_and.

primitive udp_and(y,a,b); output y; input a,b; table // a b : y 0 0 : 0; 1 0 : 0; 0 1 : 0; 1 1 : 1; endtable endprimitive

 Note: ANSI C style decalration for UDPs are also supported. This style allows the declaration of a primitive ports to be combined with the port list. E.g. primitive udp_and ( output out, input a, input b) --------endprimitive

State Table Entries

In order to understand how state table entries are specified, let us take a closer look at the state table for udp_and. Each entry in the state table in a combinational UDPs has the following pseudosyntax: <input1><input2>------<inputn>:<ouput>;

NOTE
1. The <input#> vaklues in a sttae table entry must appear in the same order As they appear in the input terminal list.It is important to keep this in mind while designing UDPs, because deasigner frequently make mistake in the input order and get incorrect result. Input and output are separated by a :. A state table entry ends with a ;. All possible combinations of inputs. Where the output produces a known value, must be explicitly specified. Otherwise, if a certain combination occur and the corresponding entry is not in the table, the output is x. use of default x output is frequently used in commercial models. Note that the table for udp_and does not handle the case when a or b is x.

2. 3. 4.

Note
The table for udp_and does not handle the case when a or b is x. Completely specify all possible cases. The values z is not allowed in a UDP. The z values on inputs are treated as x values.

primitive udp_or(y,a,b); output y; input a,b; table // a b : y 0 0 : 0; 1 0 : 0; 0 1 : 0; 1 1 : 1; x 1 : 1; 1 x : 1; endtable endprimitive

Shorthand Notation For Dont Cares

In the above example, whenever one input is 1, the result of the or operation is 1, regardless of the value of the other input. The ? Symbol is used for a dont care condition. The ? Symbol is automatically expanded to 0,1 or x. The or gate described above can be rewritten with the ? Symbol.

primitive udp_or(y,a,b); output y; input a,b; table // a b : y 0 0 : 0; 1 ? : 0; // ? Expanded to 0,1,x. ? 1 : 0; 1 1 : 1; x 1 : 1; 1 x : 1; endtable endprimitive

Instantiating UDP Primitives

UDPs are instantiated exactly like verilog gate primitives. E.g. module fulladd(sum,cout,a,b,cin); output sum,cout; input a,b,cin; wire s1,c1,c2; xor (s1,a,b); udp_and (c1,a,b); xor (sum,s1,cin); udp_and (c2,s1,cin); or (cout,c2,c1); endmodule

Program
Write a program for 4 to 1 mux.

Sequential UDPs

Sequentail UDPs have the following differnce

1. The output of a sequential UDPs is always declared as a reg. 2. An initial statement can be used to initialize output of sequential UDPs. 3. The format of a state table entry is slightly different
<input1><input2>----<inputn>:<current_state>:<next_state>;

4. There are 3 sections in a state table entry inputs, current state and next state. the 3 sections are separated by a colon(:) symbol. 5. Input specification of state table entries can be in terms of input levels or edge transitions. 6. The current state is the current value of the output register. 7. The next state is computed based on input and current state .The next state becomes the new value of the output registers. 8. All possible combinational of inputs must be specified to avoid unknown values.

 If a sequential UDP is sensitive to input levels ,it is called level sensitive sequential UDP. If a sequential UDP is sensitive to edge transition on input ,it is called edge sensitive sequential UDP.

Level Sensitive Sequential UDPs

Level sensitive UDPs change state based on input levels. Latches are the most common example of the level sensitive UDPs. Note: symbol - dash is used to denote no change in the state of the latch.

primitive d_lat(q,d,clk); output q; reg q; input d,clk; initial q = 0; table // d clk : q : q+ ? 0 : ? : -; 0 1 : ? : 0; 1 1 : ? : 1; endtable endprimitive

Edge Sensitive Sequential UDPs

Edge sensitive sequential UDPs change state based on edge transitions and input levels. Edge trigger F/F are the most common example of the edge sensitive sequential UDPs.

 E.g. primitive dff(q,d,clk); output q; reg q; input d,clk; initial q = 0; table // d clk : q : q+ (??) ?: ? : -; ? (1?): ? : -; ? (?0): ? : -; ? (0x): ? : -; ? (x1): ? : -; 0 (01): ? : 0; 1 (01): ? : 1; endtable endprimitive

Note
(10)denotes a negative edge transition from logic 1 to logic 0. (1x)denotes a transition from logic 1 to unknown x state. (0?)denotes a transition from 0 to 0,1 or x. potential positive edge transition. (??)denotes any transition in signal value 0,1,or x to 0,1 or x. only one edge specification in a single table entry is allowed.

Shorthand symbol
? b -

Meaning
0,1,x 0,1 No change in state value

explanation
Cannot be specified in an output field Cannot be specified in an output field Can be specified only in output field of a sequential UDP

r
f p n *

(01)
(01) (01),(0x) or(x0) (10),(1x) or(x0) (??)

Rising edge of signal

falling edge of signal Potential rising edge of signal Potential rising edge of signal Any value change in signal

Program
Write a program for t F/F with UDP. Write a program for jk F/F with UDP.