PHYSICAL VERIFICATION

BY VIKRAM

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Physical verification
CONTENTS

Electric rule checks

Parasitic extraction

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Physical Verification
Need for physical verification. Tools
DRC - verifies the physical integrity of the design. ERC - verifies electrical integrity of IC designs. LVS - Match the layout to the schematic design.

How it works ?
Inputs :
Layout GDSII/Cif/Database Schematic Spice/Database

Designer needs to write rules - DRC /ERC checks and LVS checks. Major Tool Vendors. :
Mentor Calibre Cadence Diva/Assura

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The Flow
Design Flow

Layer processing
DRC Connectivity Extraction

Device Extraction.
ERC LVS

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Physical Verification
Checks the design for fabrication feasibility and physical defects that could result in the design to not function properly
3 checks (DRC, ERC, and LVS)

Design Rule Checks (DRC)

Verifies that design does not violate any fabrication rules associated with the target process technology (metal width/space, antenna ratio, etc)

Electrical Rules Checks (ERC)

Verifies that there are no short or open circuits with power and ground as well as resistors/capacitors/transistors with floating nodes (part of LVS)

Layout Versus Schematic (LVS)

Final physical design matches the logical (schematic) version in terms of correct connectivity and number of electrical devices
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Hercules is the Sign-Oysical Verification

ERC
Internal operations
Operates on the connectivity netlist. Path tracing. Property verifications.

Related rule file contents

Pathchk , ( Calibre rule)
ERC SELECT CHECK X X {PATHCHK !POWER PRINT POLYGONS file1}

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Physical Verification
Checks the design for fabrication feasibility and physical defects that could result in the design to not function properly
3 checks (DRC, ERC, and LVS)

Layout Versus Schematic (LVS)

Final physical design matches the logical (schematic) version in terms of correct connectivity and number of electrical devices

Electrical Rules Checks (ERC)

Verifies that there are no short or open circuits with power and ground as well as resistors/capacitors/transistors with floating nodes (part of LVS)

Design Rule Checks (DRC)

Verifies that design does not violate any fabrication rules associated with the target process technology (metal width/space, antenna ratio, etc) Hercules is the Sign-Off Tool for Physical Verification
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Parasitic extraction
Custom design FLOW."
Schematic Entry Layout Entry Physical design verification
LVS DRC ERC

Parasitic extraction Simulation

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Parasitic extraction
Parasitic Extraction Extracts the parasitic values of each interconnect and contact that will be on the silicon wafer Parasitic Formats: SPF, RPF and DSPF The standard parasitic format ( SPF ) describes interconnect delay and loading due to parasitic resistance and capacitance. RSPF Reduced SPF. DSPF--- Detailed SPF , describes the actual parasitic resistance and capacitance components of a net.

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Parasitic extraction: RC extraction

After doing physical verification LVS & DRC parasitic capacitance, Resistance, and Devices are extracted.
It extract PMOS and NMOS with real value of stray/parasitic capacitance It extract RC of routes It extract coupling capacitance The standard parasitic format ( SPF ) describes interconnect delay and loading due to parasitic resistance and capacitance. It extract DSPF (Detailed Standard Parasitic Format) which could be used as spice file

DSPF--- Detailed SPF , describes the actual parasitic resistance and capacitance components of a net Tool used
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Xcalibre (Mentor)

Run parasitic extraction

To run parasitic extraction in open the layout view and go to StarRC | Parasitic Generation Cockpit. The setting should be automatically loaded for you as shown in Figure 14, but some options are useful to understand
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Thank You

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 QUESTIONS ?

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