Digital Integrated Circuits: A Design Perspective

Digital Integrated Circuits
2nd
Inverter
Digital Integrated
Circuits
A Design Perspective
The Inverter
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
July 30, 2002
2nd
Inverter
The CMOS Inverter: A First Glance
V
in
V
out
C
L
V
DD
2nd
Inverter
CMOS Inverter
Polysilicon
In
Out
V
DD
GND
PMOS
2
Metal 1
NMOS
Out In
V
DD
PMOS
NMOS
Contacts
N Well
2nd
Inverter
Two Inverters
Connect in Metal
Share power and ground

Abut cells
V
DD
2nd
Inverter
CMOS Inverter
First-Order DC Analysis
V
OL
= 0
V
OH
= V
DD
V
M
= f(R
n
, R
p
)
V
DD
V
DD
V
in
5 V
DD
V
in
5 0
V
out
V
out
R
n
R
p
2nd
Inverter
CMOS Inverter: Transient Response
t
pHL
= f(R
on
.C
L
)
= 0.69 R
on
C
L
V
out
V
out
R
n
R
p
V
DD
V
DD
V
in
5 V
DD
V
in
5 0
(a) Low-to-high (b) High-to-low
C
L
C
L
2nd
Inverter
Voltage Transfer
Characteristic
2nd
Inverter
PMOS Load Lines
V
DSp
I
Dp
V
GSp
=-2.5
V
GSp
=-1
V
DSp
I
Dn
V
in
=0
V
in
=1.5
V
out
I
Dn
V
in
=0
V
in
=1.5
V
in
= V
DD
+V
GSp
I
Dn
= - I
Dp
V
out
= V
DD
+V
DSp
V
out
I
Dn
V
in
= V
DD
+V
GSp
I
Dn
= - I
Dp
V
out
= V
DD
+V
DSp
2nd
Inverter
CMOS Inverter Load Characteristics
I
Dn
V
out
V
in
= 2.5
V
in
= 2
V
in
= 1.5
V
in
= 0
V
in
= 0.5
V
in
= 1
NMOS
V
in
= 0
V
in
= 0.5
V
in
= 1
V
in
= 1.5
V
in
= 2
V
in
= 2.5
V
in
= 1
V
in
= 1.5
PMOS
2nd
Inverter
CMOS Inverter VTC
V
out
V
in
0.5 1 1.5 2 2.5
0
.
5
1
1
.
5
2
2
.
5
NMOS res
PMOS off
NMOS sat
PMOS sat
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS res
PMOS sat
2nd
Inverter
Switching Threshold as a function
of Transistor Ratio
10
0
10
1
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
M

V

(
V
)

W
p
/W
n
2nd
Inverter
Determining V
IH
and V
IL

V
OH
V
OL
V
in
V
out
V
M
V
IL
V
IH
A simplified approach
2nd
Inverter
Inverter Gain
0 0.5 1 1.5 2 2.5
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
V
in
(V)
g
a
i
n
2nd
Inverter
Gain as a function of VDD
0 0.05 0.1 0.15 0.2
0
0.05
0.1
0.15
0.2
V
in
(V)
V
o
u
t

(
V
)
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
V
in
(V)
V
o
u
t
(
V
)
Gain=-1
2nd
Inverter
Simulated VTC
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
V
in
(V)
V
o
u
t
(
V
)
2nd
Inverter
Impact of Process Variations
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
V
in
(V)
V
o
u
t
(
V
)

Good PMOS
Bad NMOS
Good NMOS
Bad PMOS
Nominal
2nd
Inverter
Propagation Delay
2nd
Inverter
CMOS Inverter Propagation Delay
Approach 1
V
DD
V
out
V
in
= V
DD
C
L I
av
t
pHL
= C
L
V
swing
/2
I
av
C
L
k
n
V
DD
~
2nd
Inverter
CMOS Inverter Propagation Delay
Approach 2
V
DD
V
out
V
in
= V
DD
R
on
C
L
t
pHL
= f(R
on
.C
L
)
= 0.69 R
on
C
L
t
V
out
V
DD
R
on
C
L
1
0.5
ln(0.5)
0.36
2nd
Inverter
CMOS Inverters
Polysilicon
In
Out
Metal1
V
DD
GND
PMOS
NMOS
1.2 m
=2
2nd
Inverter
0 0.5 1 1.5 2 2.5
x 10
-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
V
o
u
t
(
V
)
Transient Response
t
p
= 0.69 C
L
(R
eqn
+R
eqp
)/2
?
t
pLH

t
pHL

2nd
Inverter
Design for Performance
Keep capacitances small
Increase transistor sizes
watch out for self-loading!
Increase V
DD
(????)
2nd
Inverter
Delay as a function of V
DD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
DD
(V)
t
p
(
n
o
r
m
a
l
i
z
e
d
)
2nd
Inverter
2 4 6 8 10 12 14
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
x 10
-11
S
t
p
(
s
e
c
)
Device Sizing
(for fixed load)
Self-loading effect:
Intrinsic capacitances
dominate
2nd
Inverter
1 1.5 2 2.5 3 3.5 4 4.5 5
3
3.5
4
4.5
5
x 10
-11
|
t
p
(
s
e
c
)
NMOS/PMOS ratio
tpLH
tpHL
tp
| = W
p
/W
n
2nd
Inverter
Impact of Rise Time on Delay
t
p
H
L
(
n
s
e
c
)
0.35
0.3
0.25
0.2
0.15
t
rise
(nsec)
1 0.8 0.6 0.4 0.2 0
2nd
Inverter
Inverter Sizing
2nd
Inverter
Inverter Chain
C
L
If C
L
is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.
In
Out
2nd
Inverter
Inverter Delay
Minimum length devices, L=0.25m
Assume that for W
P
= 2W
N
=2W

same pull-up and pull-down currents
approx. equal resistances R
N
= R
P

approx. equal rise t
pLH
and fall t
pHL
delays
Analyze as an RC network
W N
unit
N
unit
unit
P
unit P
R R
W
W
R
W
W
R R = =
|
|
.
|
\
|
~
|
|
.
|
\
|
=
1 1
t
pHL
= (ln 2) R
N
C
L
t
pLH
= (ln 2) R
P
C
L
Delay (D):
2W
W
unit
unit
gin
C
W
W
C 3 =
Load for the next stage:
2nd
Inverter
Inverter with Load
Load (C
L
)
Delay
Assumptions: no load -> zero delay
C
L
t
p
= k R
W
C
L
R
W
R
W
W
unit
= 1
k is a constant, equal to 0.69
2nd
Inverter
Inverter with Load
Load
Delay
C
int
C
L
Delay = kR
W
(C
int
+ C
L
) = kR
W
C
int
+ kR
W
C
L
= kR
W
C
int
(1+ C
L
/C
int
)
= Delay (Internal) + Delay (Load)
C
N
= C
unit
C
P
= 2C
unit
2W
W
2nd
Inverter
Delay Formula
( )
( ) ( ) / 1 / 1
~
0 int
f t C C C kR t
C C R Delay
p int L W p
L int W
+ = + =
+
C
int
= C
gin
with

~ 1
f = C
L
/C
gin
- effective fanout
R = R
unit
/W ; C
int
=WC
unit

t
p0
= 0.69R
unit
C
unit
2nd
Inverter
Apply to Inverter Chain
C
L
In Out
1 2 N
t
p
= t
p1
+ t
p2
+ + t
pN
|
|
.
|
\
|
+
+
j gin
j gin
unit unit pj
C
C
C R t
,
1 ,
1 ~
L N gin
N
i
j gin
j gin
p
N
j
j p p
C C
C
C
t t t =
|
|
.
|
\
|
+ = =
+
=
+
=
1 ,
1
,
1 ,
0
1
,
, 1

2nd
Inverter
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, C
gin,2
C
gin,N

Minimize the delay, find N - 1 partial derivatives

Result: C
gin,j+1
/C
gin,j
= C
gin,j
/C
gin,j-1

Size of each stage is the geometric mean of two neighbors

- each stage has the same effective fanout (C
out
/C
in
)
- each stage has the same delay
1 , 1 , , +
=
j gin j gin j gin
C C C
2nd
Inverter
Optimum Delay and Number of
Stages
1 ,
/
gin L
N
C C F f = =
When each stage is sized by f and has same eff. fanout f:
N
F f =
( ) / 1
0
N
p p
F Nt t + =
Minimum path delay
Effective fanout of each stage:
2nd
Inverter
Example
C
L
= 8 C
1
In
Out
C
1
1 f f
2
2 8
3
= = f
C
L
/C
1
has to be evenly distributed across N = 3 stages:
2nd
Inverter
Optimum Number of Stages
For a given load, C
L
and given input capacitance C
in

Find optimal sizing f
( )
|
|
.
|
\
|
+ = + =
f f
f
F t
F Nt t
p
N
p p
ln ln
ln
1 /
0
/ 1
0

0
ln
1 ln
ln
2
0
=

=
c
c
f
f f
F t
f
t
p p

For = 0, f = e, N = lnF
f
F
N C f C F C
in
N
in L
ln
ln
with = = =
( ) f f + = 1 exp
2nd
Inverter
Optimum Effective Fanout f
Optimum f for given process defined by
( ) f f + = 1 exp
f
opt
= 3.6
for =1
2nd
Inverter
Impact of Self-Loading on tp
1.0 3.0 5.0 7.0
u
0.0
20.0
40.0
60.0
u
/
l
n
(
u
)
x=10
x=100
x=1000
x=10,000
No Self-Loading, =0
With Self-Loading =1
2nd
Inverter
Normalized delay function of F

( ) / 1
0
N
p p
F Nt t + =
2nd
Inverter
Buffer Design
1
1
1
1
8
64
64
64
64
4
2.8
8
16
22.6
N f t
p

1 64 65

2 8 18

3 4 15

4 2.8 15.3
2nd
Inverter
Power Dissipation
2nd
Inverter
Where Does Power Go in CMOS?
Dynamic Power Consumption
Short Circuit Currents
Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
2nd
Inverter
Dynamic Power Dissipation
Energy/transition = C
L
* V
dd
2
Power = Energy/transition * f = C
L
* V
dd
2
* f
Need to reduce C
L
, V
dd
, and f to reduce power.
Vin Vout
C
L
Vdd
Not a function of transistor sizes!
2nd
Inverter
Modification for Circuits with Reduced Swing
C
L
V
dd
V
dd
V
dd
-V
t
E
0 1
C
L
V
dd
V
dd
V
t
( ) - - =
Can exploit reduced swing to lower power
(e.g., reduced bit-line swing in memory)
2nd
Inverter
Adiabatic Charging
2 2
2
2nd
Inverter
Adiabatic Charging
2nd
Inverter
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E
N
C
L
V
dd
-
2
n N ( ) - =
n(N): the number of 0->1 transition in N clock cycles
E
N
: the energy consumed for N clock cycles
P
avg
N
lim
E
N
N
-------- f
clk
- =
n N ( )
N
------------
N
lim
\ .
| |
C -
L
V
dd
-
2
f
clk
- =
o
0 1
n N ( )
N
------------
N
lim =
P
avg
= o
0 1
C -
L
V
dd
-
2
f
clk
-
2nd
Inverter
Transistor Sizing for Minimum
Energy
Goal: Minimize Energy of whole circuit
Design parameters: f and V
DD

tp s tpref of circuit with f=1 and V
DD
=V
ref
1
C
g1
In
f
C
ext
Out
TE DD
DD
p
p p
V V
V
t
f
F f
t t
|
|
.
|
\
|
|
|
.
|
\
|
+ +
|
|
.
|
\
|
+ =
0
0
1 1

2nd
Inverter
Transistor Sizing (2)
Performance Constraint (=1)

Energy for single Transition

( ) ( )
1
3
2
3
2
0
0
=
+
|
|
.
|
\
|
+ +
=
+
|
|
.
|
\
|
+ +
=
F
f
F
f
V V
V V
V
V
F
f
F
f
t
t
t
t
TE DD
TE ref
ref
DD
ref p
p
pref
p
( )( ) | |
|
.
|
\
|
+
+ +
|
|
.
|
\
|
=
+ + + =
F
F f
V
V
E
E
F f C V E
ref
DD
ref
g DD
4
2 2
1 1
2
1
2

2nd
Inverter
1 2 3 4 5 6 7
0
0.5
1
1.5
2
2.5
3
3.5
4
f
v
d
d

(
V
)
1 2 3 4 5 6 7
0
0.5
1
1.5
f
n
o
r
m
a
l
i
z
e
d

e
n
e
r
g
y
Transistor Sizing (3)
F=1
2
5
10
20
V
DD
=f(f)
E/E
ref
=f(f)
2nd
Inverter
Short Circuit Currents
Vin Vout
C
L
Vdd
I
V
D
D

(
m
A
)
0.15
0.10
0.05
V
in
(V)
5.0 4.0 3.0 2.0 1.0 0.0
2nd
Inverter
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if t
fall
>> t
rise
,
but cant do this for cascade logic, so ...
2nd
Inverter
Minimizing Short-Circuit Power
0 1 2 3 4 5
0
1
2
3
4
5
6
7
8
t
sin
/t
sout
P
n
o
r
m
Vdd =1.5
Vdd =2.5
Vdd =3.3
2nd
Inverter
Leakage
Vout
Vdd
Sub-Threshold
Current
Drain Junction
Leakage
Sub-Threshold Current Dominant Factor
Sub-threshold current one of most compelling issues
in low-energy circuit design!
2nd
Inverter
Reverse-Biased Diode Leakage
N
p
+ p
+
Reverse Leakage Current
+
-
V
dd
GATE
I
DL
= J
S
A
J
S

= 1-5pA/m
2
for a 1.2m CMOS technology
J
s
double with every 9
o
C increase in temperature
J S =10-100 pA/m2 at 25 deg C for 0.25m CMOS
J S doubles for every 9 deg C!

2nd
Inverter
Subthreshold Leakage Component
2nd
Inverter
Static Power Consumption
V
in
=5V
V
out
C
L
Vdd
I
stat
P
stat
= P
(In=1)
.V
dd
. I
stat
Dominates over dynamic consumption
Not a function of switching frequency
Wasted energy
Should be avoided in almost all cases,
but could help reducing energy in others (e.g. sense amps)
2nd
Inverter
Principles for Power Reduction
Prime choice: Reduce voltage!
Recent years have seen an acceleration in
supply voltage reduction
Design at very low voltages still open
question (0.6 0.9 V by 2010!)
Reduce switching activity
Reduce physical capacitance
Device Sizing: for F=20
f
opt
(energy)=3.53, f
opt
(performance)=4.47
2nd
Inverter
Impact of
Technology
Scaling
2nd
Inverter
Goals of Technology Scaling
Make things cheaper:
Want to sell more functions (transistors)
per chip for the same money
Build same products cheaper, sell the
same part for less money
Price of a transistor has to be reduced
But also want to be faster, smaller,
lower power
2nd
Inverter
Technology Scaling
Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating
frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per
generation
Technology generation spans 2-3 years
2nd
Inverter
Technology Generations
2nd
Inverter
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
186 177 171 160 130 106 90 Max P power [W]
1.4
1.2
6-7
1.5-1.8
180
1999
1.7
1.6-1.4
6-7
1.5-1.8
2000
14.9
-3.6
11-3 7.1-2.5 3.5-2 2.1-1.6
Max frequency
[GHz],Local-Global
2.5 2.3 2.1 2.4 2.0 Bat. power [W]
10 9-10 9 8 7 Wiring levels
0.3-0.6 0.5-0.6 0.6-0.9 0.9-1.2 1.2-1.5 Supply [V]
30 40 60 90 130
Technology node
[nm]
2014 2011 2008 2004 2001
Year of
Introduction
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
2nd
Inverter
Technology Evolution (1999)
2nd
Inverter
ITRS Technology Roadmap
Acceleration Continues
2nd
Inverter
Technology Scaling (1)
Minimum Feature Size
1960 1970 1980 1990 2000 2010
10
-2
10
-1
10
0
10
1
10
2
Year
M
i
n
i
m
u
m

F
e
a
t
u
r
e

S
i
z
e

(
m
i
c
r
o
n
)
2nd
Inverter
Number of components per chip
2nd
Inverter
Propagation Delay
t
p
decreases by 13%/year
50% every 5 years!
2nd
Inverter
(a) Power diss ipation vs. year.
95 90 85 80
0.01
0.1
1
10
100
Year
P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n

(
W
)
x
4

/

3

y
e
a
r
s
MPU
DSP
x1
.4 / 3 years
Scaling Factor k
normalized by 4m design rule
10 1
1
10
100
1000

k

3
P
o
w
e
r

D
e
n
s
i
t
y

(
m
W
/
m
m
2
)
k

0
.7
(b) Power density vs. scaling factor.
From Kuroda
2nd
Inverter
Technology Scaling Models
Full Scaling (Constant Electrical Field)
Fixed Voltage Scaling
General Scaling
ideal model dimensions and voltage scale
together by the same factor S
most common model until recently
only dimensions scale, voltages remain constant
most realistic for todays situation
voltages and dimensions scale with different factors
2nd
Inverter

Scaling Relationships for Long Channel Devices
2nd
Inverter
Transistor Scaling
(velocity-saturated devices)
2nd
Inverter
Processor Scaling
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
2nd
Inverter
Processor Power
2nd
Inverter
Processor Performance
2nd
Inverter
2010 Outlook
Performance 2X/16 months
1 TIP (terra instructions/s)
30 GHz clock
Size
No of transistors: 2 Billion
Die: 40*40 mm
Power
10kW!!
Leakage: 1/3 active Power

2nd
Inverter
Some interesting questions
What will cause this model to break?
When will it break?
Will the model gradually slow down?
Power and power density
Leakage
Process Variation

Digital Integrated Circuits: A Design Perspective

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Digital Integrated Circuits: A Design Perspective

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