Verilog HDL

Instructor : M. Umer Munir

Hardware Description Language (HDL)

Basic idea is a programming language to describe hardware Initial purpose was to allow abstract design and simulation

Design could be verified then implemented in hardware

Now Synthesis tools allow direct implementation from HDL code.

Large improvement in designer productivity

HDL

HDL allows write-run-debug cycle for hardware development.

Similar to programming software Much, much faster than design-implement-debug

Combined with modern Field Programmable Gate Array chips large complex circuits (100000s of gates) can be implemented.

HDLs

There are many different HDLs

Verilog HDL ABEL VHDL

Verilog HDL

Verilog HDL is most common

Easier to use in many ways = better for teaching C - like syntax

Developed as proprietry language in 1985 Opened as public domain spec in 1990

History

Due to losing market share to VHDL

Became IEEE standard in 1995

Abstraction Levels

Verilog is both a behavioral and a structural language. Internals of each module can be defined at four levels of abstraction, depending on the needs of the design. The module behaves identically with the external environment irrespective of the level of abstraction at which the module is described. The internals of the module are hidden from the environment. Thus, the level of abstraction to describe a module can be changed without any change in the environment. The levels are defined below.

Abstraction Levels

Behavioral or algorithmic level Dataflow level Gate level Switch level

Behavioral or algorithmic level

This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming.

Dataflow level

At this level, the module is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design.

Gate level

The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gate-level logic diagram.

Switch level

This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switch-level implementation details.

Register Transfer Level

Verilog allows the designer to mix and match all four levels of abstractions in a design. In the digital design community, the term register transfer level (RTL) is frequently used for a Verilog description that uses a combination of behavioral and dataflow constructs and is acceptable to logic synthesis tools.

Verilog HDL

Verilog constructs are use defined keywords

Examples: and, or, wire, input output

Modules have inputs and outputs Modules can be built up of Verilog primatives or of user defined submodules.

One important construct is the module

Definition of Module

Interface: port and parameter declaration Body: Internal part of module Add-ons (optional)

Some points to remember

The name of Module Comments in Verilog

One line comment (// .) Block Comment (/*.*/)

Description of Module (optional but suggested)

Description of Module

Module Structure
module module_name (port_list); port declarations

data type declarations circuit functionality

timing specifications endmodule

Module Port

Port List: A listing of the port names Example: module rca_4bit (sum, c_out , a, b); Port Types: input --> input port output --> output port inout --> bidirectional port Port Declarations: <port_type> <port_name>; Example: input [3:0] a, b; input overflow; output [3:0] out;

Data Types(1)

Net Data Type - represent physical interconnect between processes. (wire)

process process
Functional Block: FA2 (nets)

nets

Functional Block: FA1 (nets)

nets

nets

Register Data Type - represent variable to store data temporarily.

(reg) It does not represent a physical (hardware) register.
Temporary Storage

Data Type(2)

wires and registers can take one of {1, 0, x, z} : 4-valued logic x : either uninitialized variable or a conflict (ex: two signals shorted?) z : high impedance or a floating value (used for tri-state buses) Bus Declarations: <data_type> [MSB : LSB ] <signal name> ; <data_type> [LSB : MSB] <signal name> ; Examples: wire <signal name> ; wire [15:0] mult_out, adder_out; reg <signal name> ; reg [7 : 0] out ; Constants radix : B,b (binary), O,o (octal), D,d (decimal), H,h (hexadecimal) examples : 15, 4d15 (decimal 15) h15 (decimal 21, hex 15) 5b10011 (decimal 19, binary 10011) 12h01F (decimal 31, hex 01F)

Verilog Wires

Wire is an internal connection between primitives

module prim(A,B,F);

prim

A B

input A, B; output F; wire w; not (w,B); and (F,A,w); endmodule

wire

Port Connection Rules

One can visualize a port as consisting of two units, one unit that is internal to the module and another that is external to the module. The internal and external units are connected. There are rules governing port connections when modules are instantiated within other modules. The Verilog simulator complains if any port connection rules are violated. These rules are summarized in Figure.

Port Connection Rules

Verilog Operator Types

Operator Arithmetic Bitwise Reduction Logical Relational Shift Conditional Argument Result Pair of operands word Pair of operands word Single operand bit Pair of operands bit Pair of operands bit Single operand word Three operands expression

Arithmetic Operators
Operator + * / %
Operator Arithmetic

Operation Arithmetic + Arithmetic Arithmetic * Arithmetic / Modulus

Example C=A+B C=A-B C=A*B C=A/ C=A%B

Argument Result Pair of operands word

Bitwise Operators
Operator ~ & | ^ ~^ or ^~ Operator Bitwise Operation Bitwise Negation Bitwise And Bitwise Or Bitwise Exclusive-Or Bitwise Equivalence Argument Pair of operands Example C = ~A C=A&B C=A|B C=A^B C = A ~^ B Result word

Reduction Operators
Operator Operation Example & Reduction And C = &(A) ~& Reduction Nand C = ~&(A) | Or C = |(A) ~| Reduction Nor C = ~|(A) ^ Reduction Exclusive-Or C = ^(A) ~^ or ^~ Reduction Exclusive-Nor C = ~^(A) Operator Reduction Argument Single operand Result bit

Logical Operators
Operator Operation ! Logical negation && Logical and || Logical or == Logical equality != Logical inequality Example if(!A) if((A) && (B)) if((A) || (B)) if (A == B) if (A != B)

Operator Logical

Argument Result Pair of operands bit

Relational Operators
Operator Operation Example > Greater Than if (A > B) < Less Than if (A < B) >= Greater Than or Equal if (A >= B) <= Less Than or Equal if (A <= B) Operator Relational Argument Pair of operands Result bit

Other Operators
<< Left Shift A = A << 1 >> Right Shift A = A >> 3 ?: Conditional Y = A? C:D; or Event Or always @ (clk or sel) {}, {{ }} Concatenation {c_out, sum} {4{a}} = {a,a,a,a} Operator Shift Conditional Argument Single operand word Three operands Result expression

Language Rules

Case Sensitive My_input vs. my_input Space Free Upper and Lower case letters Digits Underscore Dollar Sign Variable cannot begin with Number or $ Reserved Keywords Vectors indicate more than one wire sum[3:0]

Assignments

Blocking

Non-Blocking

B = A; C = B; D = C; //A=B=C=D B <= A; C <= B; D <= C; //shift

Signal Levels
Level 0 1 z x Description Logic value 0 Logic value 1 Tri-state (high impedance) Unknown value

Radixs
Radix d b h o Description decimal binary hexadecimal octal the number 0 the decimal number 10 the binary number 10 the hex number 10 the binary number 0100 underscore _ can be inserted for readability equivalent to 8b1111_xxxx

0 10 b10 h10 4 b100 8b1000_0011 8hfx

Nested Modules
module halfadder (sum, c_out, a, b); input a, b; output sum, c_out; xor (sum, a, b); and (c_out, a, b); endmodule

Nested Modules
module fulladder (sum, c_out, a, b, c_in); input a, b, c_in; output sum, c_out; wire w1, w2, w3; halfadder HA1(w1, w2, a, b); halfadder HA2(sum, w3, c_in, w1); or (c_out, w2, w3); endmodule

The Module Interface

Port List Port Declaration

One language, Many Coding Style

One language, Many Coding Style (contd.)

One language, Many Coding Style (contd.)

Structural style: Verilog Code

Dataflow style: Verilog Code

Behavioral style: Verilog Code

Circuit to code

module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule

Adding Delays

To simulate a circuits real world behaviour it is important that propogation delays are included. The units of time for the simulation can be specified with timescale.

Default is 1ns with precision of 100ps

Component delays are specified as #(delay)

Simple Circuit with Delay

module circuit_with_delay (A,B,C,x,y);

input A,B,C;
output x,y; wire e;

and #(30) g1(e,A,B);

or #(20) g3(x,e,y);

not #(10) g2(y,C); endmodule

Effect of delay
Time (ns) <0
0 10 20 30 40 50

Input ABC 000

111 111 111 111 111 111

Output yex 101

101 001 001 010 010 011

Input signals

In order to simulate a circuit the input signals need to be known so as to generate an output signal. The input signals are often called the circuit stimulus. An HDL module is written to provide the circuit stimulus. This is known as a testbench.

Testbench

The testbench module includes the module to be tested. There are no input or output ports for the testbench. The inputs to the test circuit are defined with reg and the outputs with wire. The input values are specified with the keyword initial A sequence of values can be specified between begin and end.

Signal Notation

In Verilog signals are generalised to support multi-bit values (e.g. for buses)

The notation

A =

1b0;

means signal A is one bit with value zero.

The end of the simulation is specified with $finish.

Stimulus module for simple circuit

module stimcrct; reg A,B,C; wire x,y; circuit_with_delay cwd(A,B,C,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end endmodule

Verilog Module

Description of internal structure/function Implicit semantic of time associated with each data object/signal Implementation is hidden to outside world Communicate with outside through ports Port list is optional Achieve hardware encapsulation

module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar;

xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule

a b c_out_bar

sum

c_out

Behavioral Description
module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment
endmodule
Concatenation

a
b

Add_half

sum
c_out

Module Instantiation

Accomplished by entering

Module name as a module item within a parent module Signal identifiers at appropriate ports

Module instantiation needs a module identifier A module is never declared within another module The order of ports in instantiation usually matches the order in module declaration

Design a Full Adder

sumHA = a b c_outHA = a b sumFA = a b c_in c_outFA = a b + b c_in + a c_in sumFA = (a b) c_in c_outFA = (a b) c_in + a b

Full Adder 2 Half Adders

sumHA = a b c_outHA = a b sumFA = (a b) c_in c_outFA = (a b) c_in + a b

c_in a b Add_half ab ab

Add_half

(a b) c_in (ab)c_in

(a b) c_in + a b

Full Adder in Verilog

c_in a b Add_half

w1 ab w2 ab

Add_half

(a b) c_in w3 (ab)c_in

sum c_out

(a b) c_in + a b
module Add_full ( sum, c_out, a, b, c_in ); // parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Module instance name Add_half M1 ( w1, w2, a, b ); Add_half M2 ( sum, w3, w1, c_in ); // child module or ( c_out, w2, w3 ); // primitive instantiation endmodule

Hierarchical Modeling

Top-Down & Bottom-Up hierarchical Modeling Module basic building block in Verilog HDL functionality to the higher-level block through its port interface (inputs and outputs) = hiding the internal implementation. Instantiation creating objects from a module template
4 bit Ripple Carry Adder

Full Adder

Full Adder

Full Adder

Full Adder

XOR

AND

OR

XOR

AND

OR

XOR

AND

OR

XOR

AND

OR

Hierarchical Modeling Example

module adder4 (in1, in2, sum, c_out); input [3:0] in1, in2; output [3:0] sum; output c_out; wire c0 , c1 , c2; fulladd u1 (in1[0],in2[0], 0,sum[0],c0); fulladd u2 (in1[1],in2[1],c0,sum[1],c1); fulladd u3 (in1[2],in2[2],c1,sum[2],c2); fulladd u4 (in1[3],in2[3],c2,sum[3],c_out); endmodule
c_in = 0
In1[0] In2[0]

adder

sum[0]

In1[1] In2[1]

adder

sum[1]

In1[2] In2[2]

adder

sum[2]

module fulladd (in1, in2, carryin, sum, carryout); input in1, in2, carryin; output sum, carryout; assign {carryout, sum} = in1 + in2 + carryin;

In1[3] In2[3]

adder

sum[3]

C_out

endmodule

Modeling style & Simulation level

HDL Modeling style Behavioral Modeling - A component is described by its input/output response Structural Modeling - A component is described by interconnecting lower-level components/primitives HDL Simulation level high level : functions and algorithms RTL (register transfer level) : registers and the transfer of vectors logic level : gates and flip/flops with timing analysis (setup/hold time) switch level : transistors, resistors, wires

Behavioral Modeling

Only the functionality of the circuit, no structure No specific hardware intent For the purpose of synthesis, as well as simulation

input1, .., inputn

output1, .., outputn

if (input1) for (j=0, j<8, j=j+2) #5 output1 = 1b0; else for (j=1, j<8, j=j+2) #5 output1 = 1b1;

Structural Modeling

Functionality and structure of the circuit Call out the specific hardware For the purpose of synthesis
Higher-level Component
input1 output1

Lower-level Component1 Lower-level Component1

inputn

outputn