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PULL
DOWN
VDD
INPUT OUTPUT
VDD
B
2. BiCMOS
drain regions are doped with N-type material and substrate with P-
regions are doped with P-type material and substrate with N-type
p substrate S S
substrate connected
n transistor to GND
Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel
n substrate S substrate connected
to VDD
p transistor
- Wafer Processing
- Photolithography
- Oxide Growth & Removal
- Material Deposition & Removal
- Diffusion of Impurities
- Putting it all together
- Start with crucible of
molten silicon
(≈1425oC)
- Insert crystal seed in
melt Molten
- Slowly rotate / raise Crucible Silicon
seed to form single
crystal boule
- After cooling, slice
boule into wafers &
polish
Current
production:
200mm (10”)
Newest
technology: 300mm
(12”)
Die Single IC chip
300mm wafer
Image Source: Intel Corporation
- All dice on wafer processed simultaneously
- Each mask has one image for each die
- The basic approach:
- Add & selectively remove materials
Metal - wires
Polysilicon - gates
Oxide - insulation
Selectively diffuse impurities
Photolithography is the key
- Coat wafer with photoresist
(PR)
- Shine UV light through
mask to selectively expose
PR UV Light
FOX FOX
SiO2 Thin Oxide
Silicon Wafer Silicon Wafer
- Introduce dopant via
epitaxy or ion implant e.g. Blocking Material
Arsenic (N), Boron (P) (Oxide)
Gnd VDD
n+ n+ p+ p+
channel channel
p substrate n well
- Substrate
- Well
- Active
Areas
- Gates
- Diffusion
- Insulator
- Contacts
- Metal n well
P substrate
wafer
1. Mask Design using Layout Editor
- user specifies layout objects on different layers
- output: layout file
2. Pattern Generator
- Reads layout file
- Generates enlarged master image of each mask layer
- Image printed on glass reticle
3. Step & repeat camera
- Reduces & copies reticle image onto mask
- One copy for each die on wafer
- Note importance of mask alignment
1. The dielectric constant of SiO2 is 3.9. This gives
rise to a large coupling capacitance between
wires which has to be minimized. The solution
is to use low-k dielectrics and the proposed
materials should have approx K=3
2. Another problem arises due to small electric
field under transistor gates which has to be
maximized. The solution is to use high-k
dielectrics and the proposed materials would
have K>>4 .
- Most photolithography is done using UV with
248nm wavelength. But if the wavelength is
less than the value, it gives rise to interference
problems.
- The solution to this are:
1. Optical proximity correction (OPC)
2. Phase-shifting masks
3. Other light sources: 193nmUV, Extreme UV,
X-Rays, E-beam lithography.
- Normal mask - light spreads & overlaps
- Phase shifting mask - cancels overlap
- Drawback: requires 2 masks per litho. step
(Expensive)