Circuit families

Circuit families: Alternative CMOS logic configurations The vast majority of designs synthesize exclusively onto static CMOS libraries and even custom designs use static CMOS for 95% of the logic, high speed, low power, or density restrictions may force another solution. The most commonly used alternative circuit families are ratioed circuits, dynamic circuits, and pass- transistor circuits. The delay of a logic gate depends on its output current I, load capacitance C, and output voltage swing V, as given in following equation:

Faster circuit families attempt to reduce one of these three terms. nMOS transistors provide more current than pMOS for the same size and capacitance, so nMOS networks are preferred.

Drawback of static CMOS: - It requires both nMOS and pMOS transistors on each input, due to pMOS adding significant capacitance, has a relatively large logical effort. -All the node voltages must transition between 0 and VDD. Many faster circuit families seek to drive only nMOS transistors with the inputs, thus reducing capacitance and logical effort. An alternative mechanism must be provided to pull the output high. Determining when to pull outputs high involves monitoring the inputs, outputs, or some clock signal. Clocked circuits are often fastest if the clock can be provided at the ideal time.

Some circuit families use reduced voltage swings to improve propagation delays (and power consumption). This advantage must be weighed against the delay and power of amplifying outputs back to full levels later or the costs of tolerating the reduced swings.

Circuit Families: Static CMOS: Static CMOS circuits with complementary nMOS pull-down and pMOS pull-up networks are used for the vast majority of logic gates in integrated circuits. They have good noise margins, and are fast, low power, insensitive to device variations, easy to design, widely supported by CAD tools, and readily available in standard cell libraries. Many ASIC methodologies only allow static CMOS circuits. It is very Robust. Given the correct inputs, it will eventually produce the correct output so long as there were no errors in logic design or manufacturing. Other circuit families are prone to numerous pathologies, including charge sharing, leakage, threshold drops, and ratioing constraints. But, performance or area constraints occasionally dictate the need for other circuit families.

When a particular input is known to be latest, the gate can be optimized to favor that input. We try to build gates with equal rising and falling delays; however, using smaller pMOS transistors can reduce delay, power, and area. In processes with multiple threshold voltages, multiple flavors of gates can be constructed with different speed/leakage power tradeoffs. Bubble pushing: CMOS stages are inherently inverting, so AND and OR functions must be built from NAND and NOR gates. These relations are illustrated graphically in Figure 6.1. A NAND gate is equivalent to an OR of inverted inputs. A NOR gate is equivalent to an AND of inverted inputs. Switching between these representations is called bubble pushing.

Compound Gates: Static CMOS also efficiently handles compound gates computing various inverting combinations of AND/OR functions in a single stage. The function F = AB + CD can be computed with an ANDOR-INVERT-22 (AOI22) gate and an inverter, as shown in Figure 6.2.

Logical effort of compound gates can be different for different inputs. Figure 6.4 shows how logical efforts can be estimated for the AOI21, AOI22, and a more complex compound AOI gate, which is shown on the next slide..

Input ordering delay effect: The logical effort and parasitic delay of different gate inputs is often different. AOI21 are inherently asymmetric in that one input sees less capacitance than another. NANDs and NORs, are nominally symmetric but actually have slightly different logical effort and parasitic delays for the different inputs.

In general we define the outer input to be the input closer to the supply rail (e.g., B) and the inner input to be the input closer to the output (e.g., A). The parasitic delay is smallest when the inner input switches last because the intermediate nodes have already been discharged. Therefore, if one signal is known to arrive later than the others, the gate is fastest when that signal is connected to the inner input. Inner input has lower propagation delay.

Asymmetric Gates:

When one input is far less critical than another, even nominally symmetric gate can be made asymmetric to favor the late input at the expense of earlier one. Under ordinary conditions, the path acts as a buffer between A and Y. When reset is asserted, the path forces the output low. If reset only occurs under exceptional circumstances and can take place slowly, the circuit should be optimized for input-tooutput delay at the expense of reset. This is done by designing asymmetric NAND gate. The pMOS transistor on the reset input is also shrunk.

This reduces its diffusion capacitance and parasitic delay at the expense of slower response to reset. Perfectly symmetric NAND gate:

Skewed gates: One input transition is more important than others. Hl-skew gates to favor the rising output transition and LO-skew gates to favor the falling output transition. This favoring can be done by decreasing the size of the noncritical transistor. The logical efforts for the rising (up) and falling (down) transitions are called gu and gd, respectively, and are the ratio of the input capacitance of the skewed gate to the input capacitance of an unskewed inverter with equal drive for that transition.

Figure 6.9(a) shows how a Hl-skew inverter is constructed by downsizing the nMOS transistor. This maintains the same effective resistance for the critical transition while reducing the input capacitance relative to the unskewed inverter of Figure 6.9(b), thus reducing the logical effort on that critical transition to gu = 2.5/3 = 5/6. The improvement comes at the expense of the effort on the noncritical transition.

The degree of skewing (e.g., the ratio of effective resistance for the fast transition relative to the slow transition) impacts the logical efforts and noise margins; a factor of two is common. Skewed gates work particularly well with dynamic circuits,

What is the best P/N ratio for logic gates? The ratio giving lowest average delay is the square root of the ratio that gives equal rise and fall delays. For processes with a mobility ratio n / p = 2 as we have generally been assuming, the best ratios are shown in Figure 6.11.

Reducing the pMOS size from 2 to = 1.4 for the inverter gives the theoretical fastest average delay, but this delay improvement is only 2%. However, this significantly reduces the pMOS transistor area.

It also reduces input capacitance, which in turn reduces power consumption. Disadvantage: It leads to unequal delay between the outputs. Some paths can be slower than average if they trigger the worst edge of each gate. Excessively slow rising outputs can also cause hot electron degradation. And reducing the pMOS size also moves the switching point lower and reduces the noise margin. In summary, the P/N ratio of a library of cells should be chosen on the basis of area, power, and reliability, not average delay. For NOR gates, reducing the size of the pMOS transistors significantly improves both delay and area. Multiple Threshold Voltages: Some CMOS processes offer two or more threshold voltages. Transistors with lower threshold voltages produce more ON current, but also leak exponentially more OFF current. Libraries can provide both high- and low- threshold versions of gates.

Effect of increasing Fan in and Fan out in CMOS circuits

Each additional input to the CMOS gate needs two additional transistors. It increases chip area and total effective capacitance per gate, increasing propagation delay tp. Size scaling compensates for some ( but not all) increases in tp. By increasing device size current driving capability can be preserved, but C increases due to both increase no. of inputs and device size. Hence tp will increase with Fan-in. Practical limit of fan-in of the NAND gate is 4. To increase it we may increase in no. of cascaded stages, but this will increase delay. However, such an increase in delay can be less than increase owing to large fan-in. An increase in gate fan-out adds directly to its load capacitance and hence increases its propagation delay.

Ratio constraints occur when a node of simultaneously pulled up and down, typically by strong nMOS transistors and weak pMOS transistors. The weak transistors must be sufficiently small that the output falls below VIL of the next stage by some noise margin. Ideally the output should fall below Vt , so the next stage does not conduct static power.

Ratioed Circuits: They use use weak pull-up devices and stronger pull-down devices. They reduce the input capacitance and hence improve logical effort by eliminating large pMOS transistors loading the inputs, but depend on the correct ratio of pull-up to pull-down strength. pseudo-nMOS: Figure 6.12 shows pseudo-nMOS logic gates, which are the most common form of CMOS ratioed logic. The pull-down network is like that of a static gate, but the pull-up network has been replaced with a single pMOS transistor that is grounded so it is always ON.

The pMOS transistor width is selected to be about 1/4 the strength (i.e., 1/2 the effective width) of the nMOS pull-down network as a compromise between noise margin and speed; this best size is highly process-dependent, but is usually in the range of 1/3 to 1/6. Logical effort calculation: Suppose a complementary CMOS unit inverter delivers current I in both rising and falling transitions. For the widths shown, the pMOS transistors produce I/3 and the nMOS networks produce 4I/3. For the falling transition, the pMOS transistor effectively fights the nMOS pull-down. The output current is estimated as the pull-down current minus the pull-up current, (4I/3 - I/3) = I. Therefore, we will compare each gate to a unit inverter to calculate gd. For example, the logical effort for a falling transition of the pseudo-nMOS inverter is the ratio of its input capacitance (4/3) to that of a unit complementary CMOS inverter (3), i.e., 4/9. gu is three times as great because the current is 1/3 as much.

Parasitic delay: The pseudo-nMOS NOR has 10/3 units of diffusion capacitance as compared to 3 for a unit-sized complementary CMOS inverter, so its parasitic delay pulling down is 10/9. The pull-up current is 1/3 as great, so the parasitic delay pulling up is 10/3. pseudo-nMOS is preferred for NOR structures than NAND structures The logical effort is independent of the number of inputs in wide NORs, so pseudo-nMOS is useful for fast wide NOR gates or NORbased structures like ROMs and PLAs. Turning off the pMOS transistor can reduce power when the logic is idle. Disadvantages of ratioed circuits: Slow rising transitions, contention on the falling transitions, static power dissipation, and a non-zero VOL.

Cascode Voltage Switch Logic

Cascode Voltage Switch Logic (CVSL ) seeks the performance of ratioed circuits without the static power consumption. It uses both true and complementary input signals and computes both true and complementary outputs using a pair of nMOS pull-down networks, as shown in Figure 6.20(a).

For any given input pattern, one of the pull-down networks will be ON and the other OFF. The pull-down network that is ON will pull that output low. This low output turns ON the pMOS transistor to pull the opposite output high. When the opposite output rises, the other pMOS transistor turns OFF so no static power dissipation occurs. CVSL has a potential speed advantage because all of the logic is performed with nMOS transistors, thus reducing the input capacitance. As in pseudo-nMOS, the size of the pMOS transistor is important. A large pMOS transistor will slow the falling transition. Unlike pseudo-nMOS, the feedback tends to turn off the pMOS, so the outputs will eventually settle to a legal logic level. The CVSL gate requires both the low- and high-going transitions, adding more delay. Contention current during the switching period also increases power consumption. CVSL is poorly suited to general NAND and NOR logic. Even for symmetric structures like XORs, it tends to be slower than static CMOS, as well as more power-hungry.

Dynamic Circuits
Dynamic circuits uses a clocked pull-up transistor rather than a pMOS that is always ON. Dynamic circuit operation is divided into two modes, shown in Figure 6.22. During precharge, the clock is '0,' so the clocked pMOS is ON and initializes the output Y high. During evaluation, the clock is '1' and the clocked pMOS turns OFF. The output may remain high or may be discharged low through the pull-down network. Dynamic circuits are the fastest commonly used circuit family because they have lower input capacitance and no contention during switching. They also have zero static power dissipation. However, they require careful clocking, consume significant dynamic power, and are sensitive to noise during evaluation.

In Figure 6.21(c), if the inputs is '1' during precharge, contention will take place because both the pMOS and nMOS transistors will be ON. When the input cannot be guaranteed to be '0' during precharge, an extra clocked evaluation transistor can be added to the bottom of the nMOS stack to avoid contention as shown in Figure 6.23. The extra transistor is sometimes called a foot Figure 6.24 shows generic and unfooted gates.

Refer to following fig. the pull-down transistors' widths are chosen to give unit resistance. Precharge occurs while the gate is idle and often may take place more slowly. Therefore, the precharge transistor width is chosen for twice unit resistance. This reduces the capacitive load on the clock and the parasitic capacitance at the expense of greater rising delays. Footed gates have higher logical effort than their unfooted counterparts but are still an improvement over static logic.

There is no contention between nMOS and pMOS transistors during the input transition. Like pseudo-nMOS gates, dynamic gates are particularly well suited to wide NOR functions or multiplexers because the logical effort is independent of the number of inputs. The parasitic delay does increase with the number of inputs because there is more diffusion capacitance on the output node. Problem in dynamic circuits: monotonicity requirement. While a dynamic gate is in evaluation, the inputs must be monotonically rising. That is, the input can start LOW and remain LOW, start LOW and rise HIGH, start HIGH and remain HIGH, but not start HIGH and fall LOW.

Figure 6.26 shows waveforms for a footed dynamic inverter in which the input violates monotonicity. During precharge, the output is pulled HIGH. When the clock rises, the input is HIGH so the output is discharged LOW through the pull-down network. The input later falls LOW, turning off the pull-down network. However, the precharge transistor is also OFF so the output floats, staying LOW rather than rising as it would in a normal inverter. The output will remain low until the next precharge step. In summary, the inputs must be monotonically rising for the dynamic gate to compute the correct function. Unfortunately, the output of a dynamic gate begins HIGH and monotonically falls LOW during evaluation. This monotonically falling output X is not a suitable input to a second dynamic gate expecting monotonically rising signals, as shown in Figure 6.27. Dynamic gates sharing the same clock cannot be directly connected. This problem is often overcome with domino logic.