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SITEC ELECTRONICS #33/B OPPOSITE TO FLORENCE PUBLIC SCHOOL 2 ND BLOCK R.T.NAGAR BANGALORE-560032
D.B.RAJESH
Application Engineer
EVOLUTION IN COMPUTERS
First Computer
HISTORY OF IC DESIGN
Date 28th July. Year 1958. Components 1-Transistor, 3-Resistors, 1-Capacitor. Jack Kilby assembled those components together on one semiconductor. The worlds first integrated circuit. He received the noble Prize for this invention in October 2000.
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HISTORY OF IC DESIGN
MOORES LAW
In 1969, Gorden Moore stated that, the number of transistors per chip will double every 18 months !!!
And it is happening !!!!!!! Infact our world follows Moores Law.
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(in millions)
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PMOS
NMOS CMOS BICMOS GaAs
Less than 1%
24% 39% 0% Less than 1%
0%
4% 73% 2%
0%
Less than 1% 82% 6%
Less than 1% 1%
TYPES OF LOGIC
LOGIC
Standard Logic
ASIC
SIMPLE PLDs
CPLDs
FPGAs
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STANDARD LOGIC
ADVANTAGES -- Operating Speed is high
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PLDs
-- Prefabricated -- Defines more functions -- Reprogrammable -- Occupies less area -- Operating speed is low
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Programmable array logic (PAL) Programmable AND array with fixed OR array
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CPLD Architecture
Integration of several PLD blocks with a programmable interconnect on a single chip
I/O Block I/O Block I/O Block
SPLD Block
SPLD Block
Interconnection Matrix
I/O Block
SPLD Block
SPLD Block
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CPLD
ADVANTAGE -- Non-volatile memory
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FPGA Architecture
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IOB
IOB = Input/Output Block (interface between the package pins and the internal logic) For spartan3 400k there are totally 144 IO pins. In that 97 pins are user pins and 47pins are dedicated pins Totally 10 FRC ports are there in that 3---16pins2pins(1vcc,1gnd) 7---10pin----4pins(3vcc,1gnd)
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CLB
CLB (Configurable Logic Block) contains 4---LUT (4 variable) Each LUT contains 1) Function Generators 2) MUX 3) Flip Flop 4) Buffers
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BLOCK RAM
Used to store large amount of data. Totally 16 block rams are there in Spartan-3 FPGA Each block ram can store 18kbit data
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MULTIPLIER
Totally 16 Multipliers are there in Spartan-3 FPGA Each Multiplier will multiply two 16 bits and it will give 32bit result
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DCM
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FPGA
ADVANTAGE -- Gate density is up to 5-million
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Reprogrammable Hardware Low power High speed More I/O lines Portable
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SEMI CUSTOM
FULL CUSTOM
SEMI CUSTOM
Logic taken from libraries
FULL CUSTOM
Logic and layers are customized
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ASIC
ADVANTAGES -- Operating Speed is High -- It defines more functions -- High security
DISADVANTAGES -- One time Programmable -- Very high cost -- It takes more time to come to market. -- used for only one specific application
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Backbone of VLSI design are, Industries like. EDA Companies Mentor Graphics Synplicity Synopsys Cadence Aldec Device Vendors Xilinx, Altera , Actel, Cypress, QuickLogic etc
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DESIGN SPECIFICATIONS
Synchronous or Asynchronous design. Positive or negative edge of the clock. Number of blocks used for the design.
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DESIGN ENTRY
Design entry is the media through which ideas with designer are entered into the soft format.
There are various ways in which the design can be entered. Some of the popular ones are :
DESIGN ENTRY
SCHEMATIC HDL CODING FSM C Java
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DESIGN ENTRY
Hardware Description Languages : An effective way to describe the functionality in a user friendly manner
VHDL [ Very High Speed Integrated Circuit Hardware Description Language ]. Origin : 1981 (DOD America) Standard : IEEE1076 1999 VERILOG HDL Standard : IEEE1364
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DESIGN ENTRY
SCHEMATIC HDL CODING FSM C Java
Use library ieee; use ieee.std_logic_1164.all; entity AND4 is port ( A, B, C,D : in std_logic; S : out std_logic; ); end AND4 ; architecture AND4 _ARCH of AND4 is begin S <= (A and B) and (C and D) ; end AND4_ARCH;
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DESIGN ENTRY
SCHEMATIC HDL CODING FSM C Java
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RTL MODEL
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Simulation Purpose
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FUNCTIONAL SIMULATION
Functional Simulation is carried after entering the design. Need for the simulation comes from the fact that the entered design is working as per specifications Advantage : Saves the time consuming need for physical prototyping
A B C=1 D=1 S
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SYNTHESIS
Synthesis is automatic process of converting HDL code into equivalent logic gates. Synthesis results are Target Technology Dependent.
Use library ieee; use ieee.std_logic_1164.all; entity AND4 is port ( A, B, C,D : in std_logic; S : out std_logic; ); end AND4 ; architecture AND4 _ARCH of AND4 is begin S <= (A and B) and (C and D) ; end AND4_ARCH;
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SYNTHESIS
Constraint Design Libraries
Synthesis
Netlist
Report
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POST-SYNTHESIS SIMULATION
Post Synthesis also called as GATE Level Simulation Simulation verifies functionality after Synthesis.
Post synthesis simulation of 4-input and gate A B
C=1 D=1 S S1
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GATE DELAY
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Mapping : Tool partitions the design into the logic blocks available on the device. Good partitioning results in better performance System Partitioning
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Placing the design into the specified Device. Optimizing the usage of available resources, viz. logic cells and Interconnects.
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GATE DELAY
INTERCONNECT DELAY
BACK ANNOTATION
Writing the code effectively Change the pin assignments Change the LUT positions near to the I/O pins
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PROGRAMMING
PROGRAM & SYSTEM TEST Programming is the process of downloading the design into the device. Applicable only for PLDs After the device is programmed, you are ready to test the actual system, with real life inputs and outputs.
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VLSI - APPLICATIONS
VLSI Finds applications in all aspects of Life, Consumer Electronics, Defense, Computers, Communication, Space, Networking.. Some of applications could be listed as
WIRELESS LAN RE - CONFIGURABLE COMPUTING WEARABLE COMPUTERS HOME NETWORKING BLUETOOTH SONET / SDH Bus Interfaces, viz. PCI, Firewire, USB
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VLSI OPPORTUNITES
IBM Intel Motorola Texas Instruments ST MicroElectronics Cirrus Logic Insight [ Xilinx] Philips Sanyo Lucent
Logic Eastern Sasken GE HCL SCL Synopsys PMC Sierra NitAl IKOS Alliance Semiconductor
Wipro L&T DCM Mos Chip Chip Engines U&I Scotty Sage Avant Cirrus Logic Cadence
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JOB AVENUES
More than 700 companies in India working in VLSI design More then 200 Companies in Bangalore itself. Major Hubs - Bangalore, Delhi, Hyderabad, Chennai, Pune, Mumbai. Salaries in the range of 2 to 4 lacs/annum. Jobs are for Design Engineer, Test Engineer, Field Application Engineers, Backend .
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THANK YOU
D.BASAVA RAJESH SITEC ELECTRONICS Email : rajesh@chipmaxindia.com Mobile : 09986071743
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