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Evocation
Y CHART
The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not possible or too costly, then the revision of requirements and its impact analysis must be considered.
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Domains of y chart
The Y-chart (first introduced by D. Gajski) shown in the following figure illustrates a design flow for most logic chips, using design activities on
structural domain,
The circuit is seen as a composition of sub circuits and the way which are interconnected.it has both domains ie both structural and behavioral. Eg: a NAND gate implementation using transistors.
It gives the information on how the subparts that can be in the structural domain are located in two dimensional plane eg a cell that may represent the layout of a logic gate will consists of mask patterns of transistors and interconnections
Y chart representation
Architectural Design
Physical Design
Functional Design
Fabrication
Logic Design
Packaging
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System Specification
1. First step of design process is to lay down the specification of the system. 2. High level representation of the system. 3. Factors considered: a) Performance b) Functionality c) Physical dimension d) Design technique e) Fabrication technology 4. It is a compromise between market requirements, technological and economical viability.
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specifications of
1. 2. 3. 4.
Functional Design
1. Main functional units of the system are identified
2. Identifies the interconnect requirements between the units 3. The area, power and other parameters of each unit are estimated 4. The behavioral aspects of the system are considered not implementation specification - multiplication needed but does not specify its hardware 5. The key idea is to specify behavior, in terms of a) Input
b) Output
c) Timing of each unit Without specifying the internal structure.
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Logic Design
Design the logic, that is, 1. Boolean expressions, 2. control flow, 3. word width, 4. register allocation, etc.
X = (AB+CD)(E+F) Y= (A(B+C) + Z + D)
The outcome is called an RTL (Register Transfer Level) description. RTL is expressed in a HDL (Hardware Description Language), such as VHDL and Verilog. This description can be used in simulation and verification. As this description consists of Boolean expressions, so they can be minimized to achieve the smallest logic design.
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Circuit Design
The purpose of the circuit design is to develop a circuit representation based on the logic design. The Boolean expression can be converted into a circuit representation by taking into consideration the speed and power requirements of the original design. Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist. Circuit simulation is used to verify the correctness and timing of component.
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4.
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Physical Design
1. 2.
The circuit representation of each component is converted into geometric representation. Convert the netlist into a geometric representation. The outcome is called a layout. Connections between different components are also expressed as a geometric pattern.
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4.
5. 6.
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Fabrication
1.
Fabrication: Process includes lithography, polishing, deposition, diffusion, etc., to produce a chip. Fabrication process consists of several steps and requires various masks. Before the chip is mass produced, a prototype is made and tested.
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3.
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1.
Packaging Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module) Each chip is then packaged and tested to ensure that it meets all the design specifications and that it functions properly.
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Netlist
Physical Design
Architectural Specification
Functional Design
Layout
Fabrication
Chips
Packaging
RTL in HDL
Circuit Partitioning
1.
A chip may contain several million transistors. So layout of the entire circuit can not be handled due to the limitation of memory space and computation power available.
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3. Factors like #blocks, block sizes, interconnection between blocks, etc., are considered. 4. The output of partitioning is a set of blocks and the interconnections between them. 5. Partitioning may be hierarchical.
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Floorplanning
This step is concerned with selecting good layout for each block as well as the entire chip. The area of each block can be estimated after partitioning based approximately on the number and type of components of that block. Interconnect area between blocks is also considered. Done by design engineer rather than CAD tools: human is better in visualization. Certain components are often required to be located at a specific position on the chip.
Deadspace
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Placement
1. 2.
The blocks are exactly positioned on the chip. The goal is to minimize the area arrangement for the blocks that allows completion of interconnections between the blocks while meeting the performance constraints. For example: routable blocks but fails timing goals.
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Placement contd.
1.
2.
3. 4.
Two phases: initial placement is created in the first phase. In second phase, initial placement is evaluated and iterative improvements are made until the layout has minimum area. Quality of placement will not be evident until the routing phase has been completed. Placement may lead to an un routable design: More space may be needed. Good routing and circuit performance heavily depends on a good placement algorithm. This is due to the fact that after the position of the block has been fixed, routing can do nothing.
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Routing
1.
2. 3.
Objectives is to complete the interconnections between modules. Routing space is partitioned into channels and switchboxes. Two phases : global routing and detailed routing.
minimize the total chip area. Advantages: Making chip smaller, wire lengths are reduced. Reduces signal delays. More chip on a small area, so manufacturing cost reduced.
But should ensure design rules. Verification Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification, reliability
verification.
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The final physical layout of a complicated circuit on a small piece of silicon is generated in a set of steps using CAD tools
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