CMOS Process Flow

Susanta Sen Institute of Radio Physics & Electronics University of Calcutta

Transistor Fabrication
Cover The with Source-Drain is completed Mask Etchtransistor exposed Poly-Si Remove Implant n-type Gate Mask dopant Deposit Poly-Si Source-Drain Gate Mask Mask Oxide Oxidize Si (Gate Oxideions formation) Crosssectional View

p-Si substrate

p-Si substrate

Top View

How to mask selective regions?

Photolithography
Photoresists
Sensitive to light Resists chemical etchants

Steps of photolithography
Spin-Coat Si surface with photoresist Bake to dry Expose and develop pattern Hard bake when necessary

Steps of Lithography:
1. Coat with Photoresist
Sprinkle Photoresist

Spin 5000 rpm 20 sec.

to Vacuum Pump

Steps of Lithography

Bring Photo Expose with mask UV light on the sample

Steps of Lithography:
Develop Exposed Photoresist
Positive Resist:
Exposed region removed

Negative Resist:
Unexposed region removed

CMOS Process
Needs both p- and n-MOS devices

p-substrate good for n-MOS

Convert some region to n-doped
n-well or n-tub Twin tub process also used

Create n-well
Growremaining Pattern Remove Diffuse Etch oxide thick n-dopant photoresist photoresist oxide oxide

p-Si Substrate

p-Si Substrate

Isolate Transistors Ready to fabricate Transistors

Define Active Areas
Deposit Pattern Form Etch Grow Cover Remove The transistors Silicon Thick thin p-transistors n-transistors Silicon Silicon photoresist oxide,deposit Oxide to form Nitride Nitride are Nitride to ready only deep fill up Poly-Si with trenches trenches photoresist and pattern & implant Gate p-dopant n-dopant

p-Si Substrate

Next
Interconnects to complete the Circuit

Prepare for Interconnect

1. interconnect 2. 3. 4. Connect Deposit Etch Fill hole contact thick with Poly cuts metal oxide 5. with metal

p-Si Substrate

Circuit Layout

What are the Masks

Active Area

Poly-Si

Contact Cut

Metallization

How to Align different levels?

Alignment Marks

Assignment 1
Design the Mask Sets for the following circuits:

2-input NAND Gate

2-input NOR Gate

Lithographic Imperfections
Undercut
Lines become narrow Disconnection

Bulge
Lines become wider Shorts to adjacent line

Misalignment between layers

Device failure

Undercut and Bulge

Misalignment
Channel short Circuit

Design Rules
Takes care of manufacturing tolerances Specifies minimum allowed dimensions
Line width Spacing between lines on same layer Spacing between lines on different layers Overlap between features where required Diffusion requires higher tolerance

Specified in terms of Scalable parameter () Design Rule Check (DRC) essential

Stick Diagram
Layout Design Problem:
Satisfy both Circuit Topology & Design Rules Overwhelming task for large design

Follow Two-step process

1. Stick Diagram
Circuit topology Cartoon representation Expand each line to rectangle Follow Design Rules

2. Layout Diagram

Stick Diagram Basics

Features represented by Lines (sticks)
Poly / Diffusion / Metal etc.

Different colours for different layers

poly
VDD

p-transistor

n-diffusion
p-diffusion
In Out

metal 1 metal 2 contact / via

n-transistor
VSS

Assignment 2
Draw Stick Diagrams for:

NAND Gates (2, 3, 4 inputs)

NOR Gates (2, 3, 4 inputs) 2 to 1 MUX

2-input XOR

Stick Diagram to Layout

Assignment 3 Draw Layouts for Stick Diagrams of Assignment 2

Layout Design Issues

Multilevel circuit
Metal to be routed over transistors Limits number of interconnects

Transistors in Series Height changes

Different height cells Difficult to abut into regular-shape layout CAD tools Placement & Routing issues

Standard Cell Concept

Standard Cell Layout

Diffusion lines Horizontal Poly-silicon lines Vertical Input/Output Ports Above & Below Cell Cells & Routing Channels in Alternate Rows

Cell 1

Cell 2

Cell 3

Cell 4

Standard Cell
Transistors arranged horizontally Extend diffusion line for more transistors Add Input Modify connections New Logic Cell height does not change

A A.B A

Assignment 4 Repeat Assignments 2 & 3 in Standard Cell Style