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Comparator
To test the equality of two numbers the following circuit can be used (two 4 bit numbers):
a 0 0 1 1 b z 0 1 1 0 0 0 1 1
a0 b0 a1 b1 a2 b2 a3 b3
XNOR
Comparator (continued)
The above circuit is very straightforward to understand considering what an XNOR gate does. The following circuit tests the inequality a>b, by first testing to see whether a3 is 1 and b3 is 0 and doing the same test for lower bits if these bits are equal.
a0 b0
a1 b1
a2 b2
a3 b3
Comparator (continued)
The 7485 is a standard comparator package with the following attributes: if (A>B) lt=0, eq=0, gt=1 if (A<B) lt=1, eq=0, gt=0 4 A if (A=B) lt=l, eq=e, gt=g B
4 l e g lt eq gt
Comparator (continued)
4 A 4 B l e g
4 lt eq gt 4
A B l e g
4 lt eq gt 4
A B l e g
4 lt eq gt 4 0 1 0
A B l e g
lt eq gt
Comparator (continued)
This comparator will first compare the 4 most significant bits of the two inputs, unless they are equal the result can be found in this first stage as a is less than b if its 4 MSB are smaller and is greater if the 4 MSB are larger. If these 4 MSB of the two numbers turn out to be equal, the comparator will recursively do the same comparison on less significant bits four by four.
Comparator (continued)
The comparators we have seen so far have been magnitude comparators, that is they only work correctly when their inputs are unsigned numbers. To be able to use the same comparators for 2s complement numbers, some glue logic needs to be used which is:
a3 b3 gt 0 1 1 0 1 3 00 0 2 1 7 01 1 6 1 5 sgt 11 0 4 0 10 0
a3 b3 lt 0 1 1 0
00 0 2 1 3
01 0 6 0 7
11 0 4 1 5
10 1
1 slt
Comparator (continued)
0 1
Max(a,b)
Half Adder
(X + Y)
Half Adder
C
Example:
+
0 0 1
0 1 0
1 1 1
1 1 0
carry X Y S
Need Full Adder (so called as it can be made from two halfadders).
X Y Z
Full Adder
(X + Y + Z)
S
C
Note: Z - carry in (to the current position) C - carry out (to the next position)
YZ
X
C
00 01 11 1 10
0 1
YZ
X
S
00 01 11 1 1 1 10 1
0 1
S
(XY)
C Z
Block diagrams.
Half Adder
Carry
(XY)
X Y
Sum
Half Adder
Carry
Code Converters
Code converters take an input code, translate to its
equivalent output code.
Input code
Code converter
Output code
K-maps:
AB CD
C 01 1 X X 1 11 10 1 X X 1 X X
AB
CD
C 01 1 11 10 1 1 B
00
00
00 01 A 11 B A
00 01 1 11 10 X
X 1
X X
X X
10 1
W
CD
X
C
CD
C 01 11 10 1 1 X X X D X X B
AB
00
01
11 10 1 1 B
AB
00
00 1 01 1 A 11 X X
00 1 01 1 A 11 X
X X D
X X
10 1
10 1
C 01 1 X X 1 D 11 10 1 X X 1 X X
AB
CD
C 01 1 11 10 1 1 B
00
00
00
00 B A
01
A 11
01 1
11 10 X X 1 D X X X X
10 1
W
CD
X
C
CD
Y = CD + C'D'
C 01 11 10 1 1 X X X D X X B 00
AB
00
01
11 10 1 1 B
AB
00 1 01 1 A 11 X X
00 1 01 1 A 11 X
Z = D'
X X D
X X
10 1
10 1
C5
C1
Black-box view of 4-bit parallel adder
S4 S3 S2 S1
Si = Xi Yi Ci
Y3 X3
C3
Y2 X2
C2
Y1 X 1
C5
FA
FA
FA
FA
C1
S4
Input
Output
S3
S2
S1
Parallel Adders
Note that carry propagated by cascading the carry from
one full adder to the next.
Block-level circuit:
BCD code
X4 X3 X2 X1 0 0 1 1
unused Cout
Y4 Y3 Y2 Y1
S4 S3 S2 S1
Excess-3 code
X12..X9 Y12..Y9
4 4
X8..X5
4
Y8..Y5
4
X4..X1
4
Y4..Y1
4
C17
4-bit // adder
4
C13
4-bit // adder
4
C9
4-bit // adder
4
C5
4-bit // adder
4
C1
S16..S13
S12..S9
S8..S5
S4..S1
S4 .. S1
16-bit parallel adder ripples carry from one 4-bit block to the next. Such ripple-carry circuits are slow because of long delays needed to propagate the carries.
Recall that:
X-Y = X + (-Y) = X + (2s complement of Y) = X + (1s complement of Y) +1 X+Y = X + (Y)
such that: output = Y when S=0 = Y' when S=1 (ii) S connected to carry-in.
Cout
Cin
Analysis: If S=1, then X + (1's complement of Y) +1 appears as the result. If S=0, then X+Y appears as the result.
S4 S3 S2 S1
Revision
C 0 0 0 1 S 0 1 1 0
y 0 1 0 1
S Input bits
X
Y
S
Cout
Sum
Carry
Output bits
S = xy' + x'y
x' y' x y
S = (C+x'y')' C
C x y
S = (x+y)(x'+y')
S=xy C
S Input bits
yz x
A B Cin
S Cout
yz x
Sum Carry
Output bits
00 01 11 10
1
00 01 11 10
1 1
1 1 1 1 C = xy + xz + yz
x y
x y S = (xy)z xy C = xy + (xy)z
Revision
C4
C5 Binary no. A Binary no. B Input carry FA FA
C3
FA
C2
FA C1
S
S 4-bit sum
S4
S3
S2
S1
table!
X12..X9 Y12..Y9
4 4
X8..X5
4
Y8..Y5
4
X4..X1
4
Y4..Y1
4
C17
4-bit // adder
4
C13
4-bit // adder
4
C9
4-bit // adder
4
C5
4-bit // adder
4
C1
S16..S13
S12..S9
S8..S5
S4..S1
Voter 2
Voter 3
1 2 3 4 1 2 3 4
S
A
S
B
1 2 3 4
3-bit Output
Cout
Cin
Parallel adder
Full-adder 2
X4 X3 X2 X1
Z4 Z3 Z2 Z1
Zi = S.Yi' + S'.Yi
When S=0, Cin=0, Zi = Yi S = X + Y When S=1, Cin=1, Zi = Yi' S = X + Y' + 1
Cout
Cin
S4 S3 S2 S1
x3
A3.B3'
(A < B)
x1 A3.B3' + x3.A2.B2' + x3.x2.A1.B1' + x3. x2.x1.A0.B0' A0 B0 (A = B) x3. x2.x1.x0 x0 (A > B)
0 1 1 0 1 0 1 0
A3 A2 A1 A0 B3 B2 B1 B0
4-bit comp
(A < B) (A > B) (A = B)
1 0 0
Propagation Delay
Every logic gate experiences some delay (though very
small) in propagating signals forward.
This delay is called Gate (Propagation) Delay. Formally, it is the average transition time taken for the
output signal of the gate to change in response to changes in the input signals.
Propagation Delay
Input Output
Input
L H L tPHL tPLH
Output
Propagation Delay
A B C
Ideally, no
delay:
1
0 1 0 1 0
Signal for A
Signal for A
0 1 0
If inputs are stable at times t1,t2,..,tn, respectively; then the earliest time in which the output will be stable is: max(t1, t2, .., tn) + t
To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.
S
t 2t
max(t,2t)+t = 3t
C5
FA
FA
FA
FA
C1
S4
S3
S2
S1
0 0 mt
Full Adder
Si Ci+1
Si
t
max(t,mt)+t max(t,mt)+2t
Ci+1 Ci
mt
as their delay times. Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles. Maximum Delay: ((n-1)*2+3)t
Faster Circuits
Three ways of improving the speed of these circuits:
(i) Use better technology (e.g. ECL faster than TTL gates), BUT (a) faster technology is more expensive, needs more power, lower-level of integrations. (b) physical limits (e.g. speed of light, size of atom). (ii) Use gate-level designs to two-level circuits! (use sum-
of-products/product-of-sums) BUT
(a) complicated designs for large circuits. (b) product/sum terms need MANY inputs!
where intermediate signals are labelled as Pi, Gi, and defined as:
Pi = XiYi Gi = Xi.Yi
Ci Pi Gi
Ci+1
Pi+1
Ci+2 Gi+1
delay. Can reduce delay by expanding and flattening the formula for carries. For example, Ci+2
Ci+2 = Gi+1 + Pi+1.Ci+1 = Gi+1 + Pi+1.(Gi + Pi.Ci ) = Gi+1 + Pi+1.Gi + Pi+1.Pi.Ci
Notice that formulae gets longer with higher carries. Also, all carries are two-level sum-of-products expressions, in terms of the generate signals, Gs, the propagate signals, Ps, and the first carry-in, Ci.
Maximum propagation
delay is 4t (t to get generate & propagate signals, 2t to get the carries and t for the sum signals) where t is the average gate delay.
Binary Multipliers
The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding
0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 9 2 0 2 4 6 8 10 12 14 16 18 3 0 3 6 9 12 15 18 21 24 27 4 0 4 8 12 16 20 24 28 32 36 5 0 5 10 15 20 25 30 35 40 45 6 0 6 12 18 24 30 36 42 48 54 7 0 7 14 21 28 35 42 49 56 63 8 0 8 16 24 32 40 48 56 64 72 9 0 9 18 27 36 45 54 63 72 81
0 0
1 0
Binary Multiplication
0 0 0 1 0 1 Binary multiplication is implemented using the same basic longhand algorithm that you learned in grade school. A3 x B3 A3B0 A3B1 A3B2 A2B2 A1B3 A2B1 A1B2 A0B3
X 0 1
A2 B2
A2B0 A1B1 A0B2
A1 B1 A1B0 A0B1
A0 B0 A0B0
A3B3
A2B3
Easy part: forming partial products (just an AND gate since B I is either 0 or 1) Hard part: adding M, N-bit partial products
Comp 411 Spring 2008 02/26/2008 L11 Multiplication Division 59
Multiplication: Implementation
Multiplicand Shift left 64 bits
Multiplier0 = 1 1. Te st Multiplier0 Multiplier0 = 0 Sta rt
64-bit ALU
Control test
1a. Add multiplicand to product and place the re sult in Product re gi ster
32nd repetition?
Ye s: 32 repetitio ns
Done
02/26/2008
Second Version
Start Mul ti pli cand 32 bits Multiplier0 = 1 32-bit ALU Mul tiplier Shift right 32 bits 1. Test Multiplier0 Multiplier0 = 0
Pro duct
64 bits
Control test
1a. Add multiplicand to the le ft half of the product and place the re sult in the le ft half of the Product register
32nd repetition?
No : < 32 repetitions
Yes: 32 repetitions
Done
02/26/2008
2
3 4
0010
0010 0010
02/26/2008
Final Version
Start
Multiplicand 32 bits
Product0 = 1 1. Test Product0 Product0 = 0
32-bit ALU
1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register
Product 64 bits
Control test
The trick is to use the lower half of the product to hold the multiplier during the operation.
32nd repetition?
Yes: 32 repetitions
Done
02/26/2008
02/26/2008
Faster Multiply
A1 & B A0 & B
A2 & B
A2 & B
A31 & B
P32-P63
P31
P2
P1
P0
02/26/2008
HA
S
A B Co
HA
S
A B Co
HA
S
A B Co
HA
S
A B
These Adders can be removed, and the AND gate outputs tied directly to the Carry inputs of the next stage.
This small improveme nt in performanc e hardly seems worth the effort, however, this design is easier to pipeline.
02/26/2008
Division
Start 1. Subtract Divisor from the Remainder leave the result in the Remainder >=0 <0
Test Remainder
Restore Remainder by adding Divisor Shift Quotient to the left set its rightmost bit = 0
Repeat 33 times
02/26/2008
Digital Logic
7400 Series parts found in the evaluation lib:
7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7416 7417 7420 7422 Quadruple 2-input Positive-Nand Gates Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs Quadruple 2-input Positive-Nor Gates Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs Hex Inverters Hex Inverters with Open-Collector Outputs Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs Hex Buffers/Drivers with Open-Collector High-Voltage Outputs Quadruple 2-input Positive-And Gates Quadruple 2-input Positive-And Gates with Open-Collector Outputs Triple 3-input Positive-Nand Gates Triple 3-input Positive-And Gates Triple 3-input Positive-Nand Gates with Open-Collector Outputs Dual 4-input Positive-Nand Schmitt Triggers Hex Schmitt-Trigger Inverters Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs Hex Buffers/Drivers with Open-Collector High-Voltage Outputs Dual 4-input Positive-Nand Gates Dual 4-input Positive-Nand Gates with Open-Collector Outputs
69
Lecture #8
72
Thank You